Prototype characterization of a charge-integration pixel detector readout chip with in-pixel A/D conversion

Li, M.; Wei, W.; Jiang, X. S.; Cui, Shiyong; Zhang, J.; Lü, Bin; Liu, Z.

doi:10.1088/1748-0221/17/01/p01003

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…Two prototype chips of HYLITE have been manufactured and fully tested. HYLITE0.1 validated the pixel functionality [4]. HYLITE0.2 verified the executability of the in-array distributed LDOs [5].…”

Section: Introductionmentioning

confidence: 84%

Optimized design and characterization of HYLITE, a charge-integration readout chip of XFEL

Li,

Wei,

Jiang

et al. 2024

J. Inst.

Self Cite

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HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel readout chip designed for SHINE (Shanghai HIgh repetition rate XFEL aNd Extreme light facility). The target specifications for the full-size HYLITE chip include a pixel matrix of 128 × 128 pixels and a frame rate of 10 kHz. In order to meet these specifications, two small-scale chips, designated HYLITE0.1 and HYLITE0.2, were fabricated and underwent comprehensive testing. Some issues were discovered during tests including the noise performance and the error of output ADU (Analog Digital Units) codes. The HYLITE200S represents the third prototype chip developed to address the above issues. The CDS (Correlated Double Sampling) circuits and glitch-clear clock structures are integrated in pixels. Furthermore, to meet the data output rate requirements of the full-size chip, a high-speed data interface has been designed. Test results show that the signal-to-noise ratio is improved to 9.31 for a 12 keV single photon, and the ADU error is fixed. By integrating a phase-locked loop and a balanced encoding logic, the data interface can work steadily at a speed of 3.125 Gbps.

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Section: Introductionmentioning

confidence: 84%

Optimized design and characterization of HYLITE, a charge-integration readout chip of XFEL

Li,

Wei,

Jiang

et al. 2024

J. Inst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…The pixel structure of HYLITE0.2 is mostly inherited from HYLITE0.1 [8]. As illustrated in figure 2, the pixel includes a charge sensitive preamplifier (CSA) stage, the gain-switching circuits, an in-pixel ADC and a calibration block.…”

Section: Pixel Structurementioning

confidence: 99%

“…Two sub-blocks are included: a voltage calibration block which is controlled by external signals and a current calibration block which acts like an internal current source. Details of the calibration block can be found in [8].…”

Section: Pixel Structurementioning

confidence: 99%

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A charge-integration pixel readout chip features IR-drop effect mitigation by distributed LDOs

Li¹,

Wei²,

Jiang³

et al. 2022

J. Inst.

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HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel detector readout chip, which is designed for SHINE (Shanghai high repetition rate XFEL and extreme light facility). The targeting pixel array of a full-size chip is 128 × 128 with a pixel pitch of 100 μm. The dynamic range of HYLITE is 1 ∼ 10000 photons at 12 keV, and the frame rate is 10 kHz. Large array size, high dynamic range, and high readout speed result in a big challenge of large power consumption and a significant IR-Drop effect. We implemented HYLITE0.2, which is the second prototype chip fabricated in a CMOS 130 nm process. Compared with HYLITE0.1, HYLITE0.2 aims to implement a full-function chip with a further shrunk pixel size, while the foreseen problem of severe IR-Drop effect of the full-size chip must be solved. To mitigate the IR-Drop effect, we proposed a novel architecture of distributed in-array Low-Dropout Regulators (LDOs). The pixel array consists of 16 × 24 pixels, and the full functionality was implemented within a pixel pitch of 100 μm. Measurements show that pixels powered by the proposed architecture work well, and the gain gradient of those pixels is 31.8% of the pixels powered by the conventional architecture.

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A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

Wei

Zhang

et al. 2022

NUCL SCI TECH

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Prototype characterization of a charge-integration pixel detector readout chip with in-pixel A/D conversion

Cited by 5 publications

References 10 publications

Optimized design and characterization of HYLITE, a charge-integration readout chip of XFEL

Optimized design and characterization of HYLITE, a charge-integration readout chip of XFEL

A charge-integration pixel readout chip features IR-drop effect mitigation by distributed LDOs

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

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