2022
DOI: 10.1007/s11664-022-09503-z
|View full text |Cite
|
Sign up to set email alerts
|

Protrusion of Through-Silicon-Via (TSV) Copper with Double Annealing Processes

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3

Citation Types

0
3
0

Year Published

2022
2022
2024
2024

Publication Types

Select...
5
1

Relationship

0
6

Authors

Journals

citations
Cited by 11 publications
(3 citation statements)
references
References 65 publications
0
3
0
Order By: Relevance
“…In recent years, three-dimensional (3D) integrated circuit (IC) technology with the through-silicon via (TSV) has attracted significant attention because of its versatility, small size, and high performance. 3D IC is a technology that reduces the overall wire length and delay by vertically stacking multiple chips through high-density chip-to-chip interconnects [1][2][3][4][5][6][7] . TSV technology involves several processes, including etching holes in Si chips, depositing insulating/blocking/seeding layers, filling blind holes with Cu conductors, removing the backside Si and Cu overlay films via chemical-mechanical planarization (CMP) to expose Cu microcartridges, and ball bonding 8,9 .…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…In recent years, three-dimensional (3D) integrated circuit (IC) technology with the through-silicon via (TSV) has attracted significant attention because of its versatility, small size, and high performance. 3D IC is a technology that reduces the overall wire length and delay by vertically stacking multiple chips through high-density chip-to-chip interconnects [1][2][3][4][5][6][7] . TSV technology involves several processes, including etching holes in Si chips, depositing insulating/blocking/seeding layers, filling blind holes with Cu conductors, removing the backside Si and Cu overlay films via chemical-mechanical planarization (CMP) to expose Cu microcartridges, and ball bonding 8,9 .…”
Section: Introductionmentioning
confidence: 99%
“…Insufficient or excessive wafer polishing can lead to leaks and shorts, making the chips defective. Residual stress, interface delamination, and cracking occur when the annealing time or temperature is insufficient or excessive 6,16,17 . However, real-time nondestructive characterization methods for Cu protrusions and dishing are still limited.…”
Section: Introductionmentioning
confidence: 99%
“…In recent years, microsystem technology has received more and more attention (Fan et al , 2022; Zhang et al , 2022). Microsystems that combine micromachining technology and integrated circuit technology have the advantages of miniaturization, integration, high density and low cost (Maity et al , 2022).…”
Section: Introductionmentioning
confidence: 99%