Providing 100% throughput in memory–memory–memory switches with in‐sequence service

Gao, Ya; Qiu, Zhiliang; Zhang, Jian

doi:10.1049/iet-com.2013.0223

Cited by 5 publications

(3 citation statements)

References 16 publications

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“…For the traffic distribution model, we consider the nonuniform distribution to simulate burst traffic. This traffic model uses the probability

ω

as the fraction of input load directed to some predetermined outputs, whereas the rest of the input load is directed to all outputs with a uniform distribution.…”

Section: Simulation and Evaluationmentioning

confidence: 99%

Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high‐performance shared‐memory switches

Liu

Pan

et al. 2020

Int J Communication

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Summary Burst traffic is a common traffic pattern in modern IP networks, and it may lead to the unfairness problem and seriously degrade the performance of switches and routers. From the perspective of switching mechanism, the majority of commercial switches adopt the on‐chip shared‐memory switching architecture, and high‐speed packet buffer with efficient queue management is required to deal with the unfairness and congestion problem. In this paper, the performance of a shared‐private buffer management scheme is analyzed in detail. In the proposed scheme, the total memory space is split into shared area and private area. Each output port has a private memory area that cannot be used by other ports. The shared area is completely shared among all output ports. A theoretical queuing model of the proposed scheme is formulated, and closed‐form formulas for multiple performance parameters are derived. Through the numerical studies, we demonstrate that a nearly optimal buffer partition policy can be obtained by setting an equally small amount of private area for each queue. This work is validated by simulations as well as hardware experiments. Software simulations show that the proposed scheme performs better than existing methods, and packet dropping caused by burst traffic can be significantly reduced. Besides, a prototype of the buffer management module is implemented and evaluated in field programmable gate array platform. The evaluation shows that the proposed scheme can ensure the efficiency and fairness while keeping a high throughput in real workload.

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“…For the traffic distribution model, we consider the nonuniform distribution to simulate burst traffic. This traffic model uses the probability

ω

as the fraction of input load directed to some predetermined outputs, whereas the rest of the input load is directed to all outputs with a uniform distribution.…”

Section: Simulation and Evaluationmentioning

confidence: 99%

Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high‐performance shared‐memory switches

Liu

Pan

et al. 2020

Int J Communication

Self Cite

View full text Add to dashboard Cite

show abstract

“…where (see (12)) We can use (8)- (12) to solve state transition probability p m, k , then use (6) and (7) to solve steady-state probability π k . At last, apply the solutions to (1) and (2) to obtain the switch throughput and delay values.…”

Section: Probability Of Full Buffermentioning

confidence: 99%

“…When tested under real-trace traffic [10], CQ switches with a feasible crosspoint buffer size can realise a good performance using round robin (RR) or random scheduling algorithms. Based on the above advantages, more and more highspeed large-scale switches [11][12][13][14][15] have taken CQ switch into consideration to simplify the dispatching procedure.…”

Section: Introductionmentioning

confidence: 99%

Improved analytical model for performance evaluation of crosspoint‐queued switch under uniform traffic

2017

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In this study, a crosspoint-queued (CQ) switch that features a buffer size larger than one and employs the workconserving random scheduling algorithm under uniform Bernoulli i.i.d. traffic is investigated through both theoretical analysis and simulation. The effect of the crosspoint buffer state on switch performance is modelled and quantified. A novel method for calculating the throughput and delay of a CQ switch with a given switch size, input load, and buffer size is proposed. Compared with existing models, the proposed calculation model offers a simpler and more accurate result, and can serve as a theoretical guide in designing high-speed switch fabrics.

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Analyzing the Impact of Redundant Paths on Multistage Switch Performance

Gao

Pan

Liu

2018

Communications and Networking

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Providing 100% throughput in memory–memory–memory switches with in‐sequence service

Cited by 5 publications

References 16 publications

Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high‐performance shared‐memory switches

Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high‐performance shared‐memory switches

Improved analytical model for performance evaluation of crosspoint‐queued switch under uniform traffic

Analyzing the Impact of Redundant Paths on Multistage Switch Performance

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