Providing accurate event models for the analysis of heterogeneous multiprocessor systems

Schliecker, Simon; Rox, Jonas; Ivers, Matthias; Ernst, Rolf

doi:10.1145/1450135.1450177

Cited by 48 publications

(34 citation statements)

References 15 publications

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“…Similarly, a TX task models the execution time of the Ethernet stack and the time that is required to transmit an Ethernet frame. The processor of the gateway is assumed to schedule tasks in staticpriority preemptive (SPP) fashion (Schliecker et al 2008). The TX task has the highest priority and RX tasks have a priority proportional to their CAN identifier below the TX task.…”

Section: Cpa Gateway Modelmentioning

confidence: 99%

Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks

et al. 2015

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Due to increased bandwidth and scalability demands, Ethernet technology is finding its way into recent in-vehicle networks. Tomorrow's heterogeneous networks will feature legacy buses [e.g. controller area network (CAN) or FlexRay] as well as high-speed Ethernet devices, connected by switches and gateways. As Ethernet offers significantly larger frame sizes than CAN, the efficient transmission of CAN data over an Ethernet backbone depends heavily on the way this data is multiplexed into Ethernet frames. This article focuses on the timing impact introduced by various CAN/Ethernet multiplexing strategies at the gateways. We present a formal analysis method to derive upper bounds on end-to-end latencies for complex multiplexing strategies, which is key for the design of safety-critical real-time systems. We capture complex interdomain signal paths spanning multiple buses, gateways, and switches and show the applicability in a realistic automotive setup.

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Section: Cpa Gateway Modelmentioning

confidence: 99%

Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks

et al. 2015

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“…an upper bound on time required to process n activations of the task. This allows the computation of an output event model describing the minimum and maximum numbers of tasks completion in a specific interval as described in Henia et al (2005) and Schliecker et al (2008). The output event models are then forwarded as input event models of the dependent tasks, which are then analyzed again using the updated event models.…”

Section: Formal Timing Analysismentioning

confidence: 99%

“…The event model describing packet injection is derived from the packet injection pattern of the target, e.g. for a an injection with period P, jitter J and minimum distance d, we use (see Schliecker et al (2008)…”

Section: Model Transformationmentioning

confidence: 99%

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Modeling of Ethernet AVB Networks for Worst-Case Timing Analysis

Diemer

Rox

Ernst

2012

IFAC Proceedings Volumes

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“…Consequently, it is assumed that memory accesses over the bus take a constant amount of time to process, since no bus conflicts can occur. For multiprocessor systems with a shared communication infrastructure, however, transfer times depend on the bus load and are therefore no longer constant, causing the traditional methods to produce incorrect results [4], [5]. The main obstacle when performing timing analysis on multiprocessor systems is that the scheduling of tasks assumes that their worst-case execution times are known.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip

Rosén

Neikter

Eles

et al. 2011

2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium

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Abstract-Optimization techniques for improving the average-case execution time of an application, for which predictability with respect to time is not required, have been investigated for a long time in many different contexts. However, this has traditionally been done without paying attention to the worst-case execution time. For predictable real-time applications, on the other hand, the focus has been solely on worst-case execution time optimization, ignoring how this affects the execution time in the average case. In this paper, we show that having a good average-case delay can be important also for real-time applications for which predictability is required. Furthermore, for real-time applications running on multiprocessor systems-on-chip, we present a technique for optimizing the average case and the worst case simultaneously, allowing for a good average-case execution time while still keeping the worst case as small as possible.

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Providing accurate event models for the analysis of heterogeneous multiprocessor systems

Cited by 48 publications

References 15 publications

Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks

Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks

Modeling of Ethernet AVB Networks for Worst-Case Timing Analysis

Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip

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