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Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication networks, basic operations of every embedded application pose a challenge for precise system analysis. Current approaches to determine end-to-end latencies in parallel heterogeneous architectures either focus on system level and allow only limited task models, or focus on activities inside a component, abstracting system level influences by overestimations.In this paper, we identify feedbacks of the system behavior that directly or indirectly impact local execution. To tackle these complex interactions we present a novel technique to integrate an extended component level scheduling analysis with refined system level approaches. Bringing the different levels of abstraction together allows the analysis of a new class of interacting applications and architectures -which could not be addressed on a single level alone.On the component level, we investigate two scheduling behaviors more closely, namely stalling during external requests, and allowing context-switches to other tasks that are ready. For both, we present a precise response time analysis. Finally, we compare the scheduling techniques with respect to real-time requirements.

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Despite accuracy, analysis speed is sometimes a concern for the performance analysis of real-time systems, e.g. if to performed at runtime for online admission tests.As of today, several algorithms to compute an upper bound to the worst-case response time of a task scheduled under static priority preemptive scheduling with polynomial run-time have been proposed.Most approaches assume periodic activation of all tasks, some allow activation jitter. We generalize the approach to support convex activation patterns, by using multi-linear workload approximations and introduce the possibility to model processor availability to the task set under analysis.

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