Current on-chip and macro networks use multi-stage arbitration schemes which independently assign different resources such as crossbar inputs and outputs to individual traffic streams. To use these networks in real-time systems, their worst-case behavior must be proved analytically in order to ensure the required timing guarantees. Current analysis approaches, however, do not capture the multi-stage arbitration accurately. In this paper, we propose an analysis that maps the multi-stage arbitration to a schedulability analysis of multiprocessors with shared resources. This allows the exploitation of knowledge about the worst-case behavior of the individual traffic streams, which is required to provide nonsymmetric guarantees. Using this scheduling analysis approach, a detailed analysis solution for a common multi-stage arbitration scheme (iSLIP) is presented. Finally, we evaluate the proposed approach experimentally and compare it to previous work.

Predicting timing behaviour is essential for the design of embedded real-time systems that can switch between different operational modes at runtime. The settling time of a mode change, called mode change transition latency, is an important system parameter. Known approaches that address the problem of timing analysis for multi-mode real-time systems are restricted to applications without communicating tasks. Also, these assume that transitions are initiated only during a steady state, however, without indicating when a system executes in a steady state. In this paper, we present an analysis algorithm which gives a maximum bound on each mode change transition latency of multi-mode distributed applications thereby overcoming limitations of previous work. We explain the algorithm, prove its correctness, illustrate the steps and provide experimental data that show its usefulness.

No abstract

Despite accuracy, analysis speed is sometimes a concern for the performance analysis of real-time systems, e.g. if to performed at runtime for online admission tests.As of today, several algorithms to compute an upper bound to the worst-case response time of a task scheduled under static priority preemptive scheduling with polynomial run-time have been proposed.Most approaches assume periodic activation of all tasks, some allow activation jitter. We generalize the approach to support convex activation patterns, by using multi-linear workload approximations and introduce the possibility to model processor availability to the task set under analysis.

No abstract