Proximity coherence for chip multiprocessors

Abstract

Many-core architectures provide an efficient way of harnessing the increasing numbers of transistors available in modern fabrication processes. While they are similar to multi-node systems, they exhibit different communication latency and storage characteristics, providing new design opportunities that were previously not feasible. Traditional cache coherence protocols, although often used in many-core designs, have been developed in the context of multinode systems. As such, they seldom take advantage of the new possibilities that many-core architectures offer.We propose Proximity Coherence, a scheme in which L1 load misses are optimistically forwarded to nearby caches via new dedicated links rather than always being indirected via a directory structure. Such an optimization is made possible by the comparable cost of local cache accesses with the use of on-chip network resources. Coherency is maintained using lightweight graph structures embedded in the L1 caches. We compare our Proximity Coherence protocol to an existing directory-based MESI protocol using fullsystem simulations of a 32 core system. Our extension lowers the latency of L1 cache load misses by up to 32% while reducing the bytes transferred on the global on-chip interconnect by up to 19% for a range of parallel benchmarks. Employing Proximity Coherence provides execution time improvements of up to 13%, reduces cache hierarchy energy consumption by up to 30% and delivers a more efficient solution to the challenge of coherence in chip multiprocessors.

Cluster Cache Monitor: Leveraging the Proximity Data in CMP

“…The research works most closely related to CCM are victim or replication strategies [6,12,16,20,26,31,32], Cooperative Caching strategies [1,5,10,11,13,17,18], and to a lesser extent, hierarchical directory coherence [8,14,15,22,33,34].…”

“…CCM requires only marginal modifications of the network interface. Barrow [5] leverages the proximity data by sending requesting messages to all neighbors, which complicates the coherence protocol. Acacio [1] and Hossain [18] also introduces the concept of using the nearby data.…”

A hybrid NoC design for cache coherence optimization for chip multiprocessors

“…Cache coherence designs to exploit the proximity of data sharers have been proposed in [6,7]. Williams et.…”

“…al. [7] propose to add direct links in four directions of NoC routers to snoop sharers in direct neighbors. However, their scheme depends on specific application mapping to work and has more hardware overhead.…”

“…As a result, if the bus configurations are fixed as in [10] and [7], the effectiveness of the snooping will be compromised since the number of possible shares searched is not related to the bus length. In another word, even if we increase the length of snooping buses, the sharers found may not increase accordingly.…”