Pseudo-complementary FET logic (PCFL): a low-power logic family in GaAs

Kanan, Riad; Hochet, B.; Declercq, M.

doi:10.1109/4.508213

Cited by 18 publications

(5 citation statements)

References 7 publications

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“…Among of the integrated devices, the co-integration of n-and pchannel HFETs has attracted considerable attention for extremely low power dissipation associated with complementary logic circuit applications [1,2]. With respect to the identical transistor performances, high output current and linearity are especially essential for signal amplification in circuit applications.…”

Section: Introductionmentioning

confidence: 99%

“…The vertical monolithic integration of the heterostructure field-effect transistors (HFETs) by the continuous growth of successive layers permits the different devices to be optimized separated on the same wafer, which provides the reduction of fabrication complexity [1][2][3][4]. Among of the integrated devices, the co-integration of n-and pchannel HFETs has attracted considerable attention for extremely low power dissipation associated with complementary logic circuit applications [1,2].…”

Section: Introductionmentioning

confidence: 99%

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Characteristics of InGaP/InGaAs complementary pseudomorphic doped-channel HFETs

Tsai

2008

Solid-State Electronics

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Characteristics of InGaP/InGaAs complementary pseudomorphic doped-channel HFETs

Tsai

2008

Solid-State Electronics

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“…Complementary signals are used to replace the lack of complementary transistors, which mimics the CMOS behavior. This leads to the pseudocomplementary FET logic (PCFL), which is based only on n-channel e-mode transistors in the GaN technology [50]. Fig.…”

Section: A Digital Circuitsmentioning

confidence: 99%

Building Blocks for GaN Power Integration

Basler¹,

Reiner

Moench

et al. 2021

IEEE Access

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GaN technology is on the advance for the use in power ICs thanks to space-saving integrated circuit components and the increasing number of integrated devices. This work experimentally investigates a number of key building blocks for GaN power integration. First, an overview of the active and passives devices of the technology is given with focus on area-efficient layouts for power transistors and limitations of on-chip capacitors and inductors with comparison to other IC technologies. Digital and analog basic circuits as part of device libraries are examined and optimized with regard to area-efficiency. The NOT gates have active areas as low as 56.7 µm 2 and max. static currents of 0.12 mA with high noise margins. Further digital gates are presented. For the analog circuits, differential amplifiers and voltage reference concepts are presented and compared. Finally, GaN power integration is discussed, and integration levels are defined and described. The GaN technology is compared with other IC technologies, and future challenges and perspectives are shown. GaN power integration based on building blocks aims to exploit the full potential of the lateral GaN technology in order to compete with Si-based IC technologies in the future.INDEX TERMS Gallium nitride, integrated circuit technology, power integrated circuits, logic circuits, analog circuits

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“…The limited levels of integration of compound semiconductor (III-V) memory can be attributed largely to the absence of a manufacturable low power III-V transistor technology. Low power III-V enhancement/depletionmode NFET logic families have been proposed [121][122][123][124]. Initial III-V LSI systems can indeed use such logic styles.…”

Section: Technology Scaling Relationsmentioning

confidence: 99%

Tunnelling-based SRAM

Wagt

1999

Nanotechnology

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This paper describes the use of low-current-density tunnelling devices to obtain dense low-power (sub-100 nW/bit) compound semiconductor static random access memory (SRAM); this cell power is over two orders of magnitude lower than the best previously demonstrated in III-V materials. This same circuit topology promises orders of magnitude reduction in static power dissipation for silicon memories, assuming a suitable Si-based negative differential resistance device, at sub-pA current levels, is developed. The concept of low-standby-power tunnelling-based SRAM (TSRAM) is presented in the context of a scaling theory for all memories and a comparison is given across technologies. Experimental results for a 50 nW TSRAM gain cell using ultralow current density (~1 A cm-2) resonant tunnelling diodes and low-leakage heterostructure field-effect transistors are discussed. We describe a one-transistor TSRAM cell, verify its operation, and discuss merits of TSRAM relative to other memory types. Silicon TSRAM standby power is projected to be lower than that of conventional-style silicon SRAM or DRAM.

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Pseudo-complementary FET logic (PCFL): a low-power logic family in GaAs

Cited by 18 publications

References 7 publications

Characteristics of InGaP/InGaAs complementary pseudomorphic doped-channel HFETs

Characteristics of InGaP/InGaAs complementary pseudomorphic doped-channel HFETs

Building Blocks for GaN Power Integration

Tunnelling-based SRAM

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