Pseudopotential-based electron quantum transport: Theoretical formulation and application to nanometer-scale silicon nanowire transistors

Abstract

We present a formalism to treat quantum electronic transport at the nanometer scale based on empirical pseudopotentials. This formalism offers explicit atomistic wavefunctions and an accurate band structure, enabling a detailed study of the characteristics of devices with a nanometer-scale channel and body. Assuming externally applied potentials that change slowly along the electrontransport direction, we invoke the envelope-wavefunction approximation to apply the open boundary conditions and to develop the transport equations. We construct the full-band open boundary conditions (self-energies of device contacts) from the complex band structure of the contacts. We solve the transport equations and present the expressions required to calculate the device characteristics, such as device current and charge density. We apply this formalism to study ballistic transport in a gateall-around (GAA) silicon nanowire field-effect transistor with a body-size of 0.39 nm, a gate length of 6.52 nm, and an effective oxide thickness of 0.43 nm. Simulation results show that this device exhibits a subthreshold slope (SS) of $66 mV/decade and a drain-induced barrier-lowering of $2.5 mV/V. Our theoretical calculations predict that low-dimensionality channels in a 3D GAA architecture are able to meet the performance requirements of future devices in terms of SS swing and electrostatic control. V

Scalable atomistic simulations of quantum electron transport using empirical pseudopotentials

“…In the envelope-function approximation, a necessary additional step is the removal of spurious solutions. [7] However, our method does not admit spurious traveling solutions within (or below) the energy range spanned by the Bloch waves in the basis set, negating the need for additional filtering. Before proceeding, care must be taken to correctly normalize the traveling wavefunctions in each contact.…”

“…More recently, novel materials have been considered to improve the performance of electronic devices. For example, atomically thin monolayers, such as graphene, [1] phosphorene, [2] and transition-metal dichalcogenides, [3,4] and their ribbons, [5][6][7][8] are being actively investigated as possible replacements of silicon as the channel material in field-effect transistors. These materials have caused an additional shift from transport models based on bulkmaterial properties towards the comprehensive modeling of the atomic structure of the material.…”

Energy Filtering Effect at Source Contact on Ultra-Scaled MOSFETs

“…Therefore, it is expected that traditional FETs will continue to dominate and be scaled to the 1nm technology node for most applications [1] [7]. To avoid degradation of SS in ultrascaled transistors, it is likely that gate-all-around (GAA) structures such as nanowires will be used [1].…”

A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs

“…Currently, three-dimensional (3-D) simulations are necessary to appropriately model devices such as FinFETs or GAA-NW, due to the two-dimensional (2-D) nature of the quantum confinement, which increases the computational cost of a study [9]. There are different approaches that can be used in simulations of state-of-the-art semiconductor devices, ranging from the relatively simple and low computationally demanding drift-diffusion method [10], to extremely complex quantum mechanical approaches, such as pseudopotential-based electron quantum transport [11] or the non-equilibrium Green’s functions (NEGF) [12] formalism, that can also be coupled to empirical tight-binding models [13]. The use of fully quantum simulators is computationally prohibitive for statistical studies, being essential a trade-off between the simulation’s accuracy and the calculation time.…”