PSnAP: Accurate Synthetic Address Streams through Memory Profiles

Olschanowsky, Catherine; Tikir, Mustafa M.; Carrington, Laura; Snavely, Allan

doi:10.1007/978-3-642-13374-9_24

Cited by 11 publications

(4 citation statements)

References 25 publications

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“…PSnAP [32] is a memory access trace compression system for performance modeling and tracebased simulation of scientific applications. Its compression is based on the dynamic detection of the frequency at which strides occur along the innermost loop dimension.…”

Section: Related Workmentioning

confidence: 99%

Building a Polyhedral Representation from an Instrumented Execution

Selva

Gruber

Sampaio

et al. 2019

ACM Trans. Archit. Code Optim.

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The polyhedral model has been successfully used in production compilers. Nevertheless, only a very restricted class of applications can benefit from it. Recent proposals investigated how runtime information could be used to apply polyhedral optimization on applications that do not statically fit the model. In this work, we go one step further in that direction. We propose the folding-based analysis that, from the output of an instrumented program execution, builds a compact polyhedral representation. It is able to accurately detect affine dependencies, fixed-stride memory accesses, and induction variables in programs. It scales to real-life applications, which often include some nonaffine dependencies and accesses in otherwise affine code. This is enabled by a safe fine-grained polyhedral overapproximation mechanism. We evaluate our analysis on the entire Rodinia benchmark suite, enabling accurate feedback about the potential for complex polyhedral transformations. CCS Concepts: • Software and its engineering → Compilers;

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Section: Related Workmentioning

confidence: 99%

Building a Polyhedral Representation from an Instrumented Execution

Selva

Gruber

Sampaio

et al. 2019

ACM Trans. Archit. Code Optim.

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“…Other methods on artificial workload generation have been described [19] and reviewed [20]. PSnAP [38] separates the program structure from the memory access pattern in two phases: capture, when PSnAP generates a profile using PMaCInst [50], and replay, when it produces a synthetic trace based on the captured profile.…”

Section: Synthetic Trace Generationmentioning

confidence: 99%

Safer Program Behavior Sharing Through Trace Wringing

Dangwal

Cui

McMahan

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

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When working towards application-tuned systems, developers often find themselves caught between the need to share information (so that partners can make intelligent design choices) and the need to hide information (to protect proprietary methods or sensitive data). One place where this problem comes to a head is in the release of program traces, for example a memory address trace. A trace taken from a production server might expose details about who the users are or what they are doing, or it might even expose details of the actual computation itself (e.g. through a side channel). Engineers are often asked to make, by hand, "analogs" of their codes that would be free from such sensitive data or, may even try to describe behaviors at a high level with words. Both of these approaches lead to missed opportunities, confusion, and frustration. We propose a new problem for study, trace-wringing, that seeks to remove as much information from the trace as possible while still maintaining key characteristics of the original. We formalize this problem and show that, for a specific instance around memory traces, as little as a few thousand bits need to be shared. We demonstrate experimentally that the trace-wrung proxies behave similarly in the context of cache simulation but with bounded leakage, and examine the sensitivity of wrung traces to a class of attacks on AES encryption. CCS Concepts • Security and privacy → Information flow control.

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“…One way to gather information on memory regions for an address stream is to use binary search tree that holds the boundary addresses for memory regions and at every memory access searches for the region the memory access fits in [17]. This requires additional split and merge operations of memory regions according to some heuristics for accurate region identification.…”

Section: Bandwidth (Gb/s)mentioning

confidence: 99%

An idiom-finding tool for increasing productivity of accelerators

Carrington¹,

Tikir

Olschanowsky³

et al. 2011

Proceedings of the International Conference on Supercomputing

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Suppose one is considering purchase of a computer equipped with accelerators. Or suppose one has access to such a computer and is considering porting code to take advantage of the accelerators. Is there a reason to suppose the purchase cost or programmer effort will be worth it? It would be nice to able to estimate the expected improvements in advance of paying money or time. We exhibit an analytical framework and tool-set for providing such estimates: the tools first look for user-defined idioms that are patterns of computation and data access identified in advance as possibly being able to benefit from accelerator hardware. A performance model is then applied to estimate how much faster these idioms would be if they were ported and run on the accelerators, and a recommendation is made as to whether or not each idiom is worth the porting effort to put them on the accelerator and an estimate is provided of what the overall application speedup would be if this were done.As a proof-of-concept we focus our investigations on Gather/Scatter (G/S) operations and means to accelerate these available on the Convey HC-1 which has a special-purpose "personality" for accelerating G/S. We test the methodology on two large-scale HPC applications. The idiom recognizer tool saves weeks of programmer effort compared to having the programmer examine the code visually looking for idioms; performance models save yet more time by rank-ordering the best candidates for porting; and the performance models are accurate, predicting G/S runtime speedup resulting from porting to within 10% of speedup actually achieved. The G/S hardware on the Convey sped up these operations 20x, and the overall impact on total application runtime was to improve it by as much as 21%.

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PSnAP: Accurate Synthetic Address Streams through Memory Profiles

Cited by 11 publications

References 25 publications

Building a Polyhedral Representation from an Instrumented Execution

Building a Polyhedral Representation from an Instrumented Execution

Safer Program Behavior Sharing Through Trace Wringing

An idiom-finding tool for increasing productivity of accelerators

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