pTask: A smart prefetching scheme for OS intensive applications

Kallurkar, Prathmesh; Sarangi, Smruti R.

doi:10.1109/micro.2016.7783706

Cited by 11 publications

(3 citation statements)

References 19 publications

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“…Some pieces of prior work inserted prefetching instructions into the program code [5,8,26,37,38,53]. These proposals use an offline or online program-profiling to choose where the prefetching instructions should be added.…”

Section: Related Workmentioning

confidence: 99%

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MANA: Microarchitecting an Instruction Prefetcher

Ansari,

Golshan,

Lotfi-Kamran

et al. 2021

Preprint

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Sciences (IPM), IranL1 instruction (L1-I) cache misses are a source of performance bottleneck. Sequential prefetchers are simple solutions to mitigate this problem; however, prior work has shown that these prefetchers leave considerable potentials uncovered. This observation has motivated many researchers to come up with more advanced instruction prefetchers. In 2011, Proactive Instruction Fetch (PIF) showed that a hardware prefetcher could effectively eliminate all of the instruction-cache misses. However, its enormous storage cost makes it an impractical solution. Consequently, reducing the storage cost was the main research focus in the instruction prefetching in the past decade.Several instruction prefetchers, including RDIP and Shotgun, were proposed to offer PIF-level performance with significantly lower storage overhead. However, our findings show that there is a considerable performance gap between these proposals and PIF. While these proposals use different mechanisms for instruction prefetching, the performance gap is largely not because of the mechanism, and instead, is due to not having sufficient storage. Prior proposals suffer from one or both of the following shortcomings: (1) a large number of metadata records to cover the potential, and (2) a high storage cost of each record. The first problem causes metadata-miss, and the second problem prohibits the prefetcher from storing enough records within reasonably-sized storage.In this paper, we make the case that the key to designing a powerful and cost-effective instruction prefetcher is choosing the right metadata record and microarchitecting the prefetcher to minimize the storage. We find that high spatial correlation among instruction accesses leads to compact, accurate, and minimal metadata records. We also show that chaining these records is an effective way to enable robust and timely prefetching. Based on the findings, we propose MANA, which offers PIF-level performance with 15.7× lower storage cost. MANA outperforms RDIP and Shotgun by 12.5 and 29%, respectively. We also evaluate a version of MANA with no storage overhead and show that it offers 98% of the peak performance benefits.CCS Concepts: • Computer systems organization → Architectures.

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Section: Related Workmentioning

confidence: 99%

“…However, the proposed prefetcher is impractical because of its high storage cost. Nonetheless, PIF motivated many researchers to develop effective and storage-efficient prefetchers [8,26,28,[32][33][34].…”

Section: Introductionmentioning

confidence: 99%

MANA: Microarchitecting an Instruction Prefetcher

Ansari,

Golshan,

Lotfi-Kamran

et al. 2021

Preprint

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show abstract

“…To ensure timeliness, it estimates the latency of cache miss operations and entangles them to prior instructions that are sufficiently far in the past to ensure timeliness of prefetches. Similar to Shotgun, two previously proposed techniques, pTask [27] and RDIP [8], also leverage global control flow information for prefetching. pTask initiates prefetching only on OS context switches and requires software support.…”

Section: Related Workmentioning

confidence: 99%

Shooting Down the Server Front-End Bottleneck

Kumar

Grot

2020

ACM Trans. Comput. Syst.

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The front-end bottleneck is a well-established problem in server workloads owing to their deep software stacks and large instruction footprints. Despite years of research into effective L1-I and BTB prefetching, state-of-the-art techniques force a trade-off between metadata storage cost and performance. Temporal Stream prefetchers deliver high performance but require a prohibitive amount of metadata to accommodate the temporal history. Meanwhile, BTB-directed prefetchers incur low cost by using the existing in-core branch prediction structures but fall short on performance due to BTB’s inability to capture the massive control flow working set of server applications. This work overcomes the fundamental limitation of BTB-directed prefetchers, which is capturing a large control flow working set within an affordable BTB storage budget. We re-envision the BTB organization to maximize its control flow coverage by observing that an application’s instruction footprint can be mapped as a combination of its unconditional branch working set and, for each unconditional branch, a spatial encoding of the cache blocks around the branch target. Effectively capturing a map of the application’s instruction footprint in the BTB enables highly effective BTB-directed prefetching that outperforms the state-of-the-art prefetchers by up to 10% for equivalent storage budget.

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The Conception of Strings Similarity in Software Engineering

Frenkel

Zakharov

2021

Communications in Computer and Information Science

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pTask: A smart prefetching scheme for OS intensive applications

Cited by 11 publications

References 19 publications

MANA: Microarchitecting an Instruction Prefetcher

MANA: Microarchitecting an Instruction Prefetcher

Shooting Down the Server Front-End Bottleneck

The Conception of Strings Similarity in Software Engineering

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