PTC-Based Sigma-Delta ADCs for High-Speed, Low-Noise Imagers

Abstract

This paper presents a novel column-parallel readout circuit for image sensors based on incremental-sigma-delta (ISD) ADCs. The excessive number of clock cycles needed per conversion is addressed. We apply the Photon Transfer Curve (PTC) based conversion to a second-order ISD ADC, achieving a 2.75x clock cycles reduction when compared to a standard secondorder ISD ADC while maintaining the same noise performance. This results in the reduction of the pixel readout time and of the size of the digital filter.

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

“…Another ADC that is becoming popular in CIS is the incremental (I) [16], [35]- [42]. The amount of cycles is dependent on the order (N order ) and resolution of the quantizer (N Q ).…”

A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator

“…M7 is a load and M6 is a driver for current sink load inverter. The output of the M2 transistor was boosted using current source represented as M6 transistor [26].…”

“…Several existing techniques in ΔΣ ADC architecture reduce the power consumption at the cost of speed [25][26][27][28][29]. Hence the performance of ADC can be improved by transferring the signal processing task to digital domain and by applying proper scaling methodology.…”

Time-to-Digital Conversion

“…Typically, single-stage op-amp architectures are chosen due to their good trade-off in power, speed, and noise performance [17]. To achieve sufficient gain, single-stage cascode op-amp topologies are typically used [18]. Given their low output voltage swing, these topologies are well compatible with FF modulators.…”

“…An ISD ADC with second-order FF modulator implementing a PTC-based conversion has been proposed by [18] and works as follows. Ideally, the ADC resolution N in bits provided by the second-order digital filter is…”