This paper presents a novel column-parallel readout circuit for image sensors based on incremental-sigma-delta (ISD) ADCs. The excessive number of clock cycles needed per conversion is addressed. We apply the Photon Transfer Curve (PTC) based conversion to a second-order ISD ADC, achieving a 2.75x clock cycles reduction when compared to a standard secondorder ISD ADC while maintaining the same noise performance. This results in the reduction of the pixel readout time and of the size of the digital filter.

No abstract

A CMOS fractional-N transmitter ofsers up to 115.2 kbit/s 2-FSK communications in the 315, 433, 868 and 915MHz ISM bands. Transmission is done using direct digital modulation of a fully integrated A Z fractional-N PLL frequency synthesizer. The high PLL bandwidth ensures a low close-in phase noise, enabling narrowband transmission with low adjacent channel power. The 5.4 mm2 IC is integrated in a 0 . 3 5~ CMOS technology and consumes 14 mA at 2.7 V. IntroductionIn many application areas, wireIess communication is moving towards higher bandwidths and higher data rates. At the same time however, a new market is emerging for low data rate, low power wireless networks that can be built at a very low cost. Typical applications range from intelligent remote control functions to sensor networks and personal area networks (PAN). The required battery life time in these applications is usually more than one year. These new markets bring new life and new requirements to the use of the unlicensed ISM bands below 1 GHz. Whereas in the past, applications in the ISM bands have mainly been limited to applications that transmit at a fixed frequency (like e.g. remote controls for cars, garage door openers, etc.), the next phase will consist of different devices that are communicating in a network configuration. New devices operating in these bands therefore need to have multi-channel capabilities along with a high spectral purity. After all, given the huge amount of channels that reside in these bands, any adjacent channel disturbance must be reduced to a minimum to ensure a reliable communication.The selection of a suitable architecture for these applications is significantly different from many other wireless applications like e.g. Bluetooth or WLAN. The very low cost requirement, and especially the narrowband operation lead to this difference. Low cost implies the use of a highly integrated architecture in a CMOS technology that is not the most advanced on the market. In this case, a 0.35pm CMOS technology has been selected for RF operation up to 1 GHz. This leads to a significant cost reduction because the IC is predominantly analog and contains only a limited amount of digital functionality. The narrowband operation puts stringent requirements on the close-in phase noise performance of the synthesizer. The use of a fractional-N architecture, which allows a PLL bandwidth higher than the modulation bandwidth, is the solution that is proposed here. Transmitter ArchitectureThe transmitted signal frequency is generated by direct digital modulation of a AE fractional-N PLL frequency synthesizer ( Figure 1) [I]. The instantaneous fractional division number in the PLL is the sum of a digital word representing the division factor of the selected channel and a word representing the instantaneous frequency deviation. The sign of this word is changed according to the incoming data bits. A digital AX modulator converts this fractional number into an oversampled bit stream whose average is equal to the fractional number. When this single b...

No abstract

To adjust the light spectrum of a flash lamp, the current flowing through the flash lamp has to be controlled. An optimal design of a switched resistor bank circuit following a predefined current profile is presented. The optimal values of the switched resistors are calculated using multi-objective optimization with genetic algorithms.