2016
DOI: 10.1088/0268-1242/31/12/124002
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Pulse quenching induced by multi-collection effects in 45 nm silicon-on-insulator technology

Abstract: This paper presents the analysis of pulse quenching effects induced in silicon-on-insulator (SOI) technology. Simulation results emphasize the need to consider multi-collection effects in the occurrence mechanisms of single event transients (SET) in very large scaling integration (VLSI) components even with SOI technologies, which is known to be initially less sensitive to soft errors (SE). The impacts of gate-to-gate spacing and voltage scaling on the SET occurrence and characteristics have been highlighted. … Show more

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Cited by 7 publications
(5 citation statements)
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“…The modeling of the charge diffusion accounts for the ambipolar diffusion mechanisms and recombination processes [16]. The modeling of the charge collection accounts for the dynamic transport and the multi-charge collection mechanisms (charge sharing, pulse quenching [13] [16]), the bias voltage, the layout, the bipolar amplification, the shallow trench isolation (STI) and the fabrication process. In the case of this work, the low substrate coupling effect induced by the bulk FinFET technology is taking into account at electrical level.…”
Section: See Prediction Toolmentioning
confidence: 99%
“…The modeling of the charge diffusion accounts for the ambipolar diffusion mechanisms and recombination processes [16]. The modeling of the charge collection accounts for the dynamic transport and the multi-charge collection mechanisms (charge sharing, pulse quenching [13] [16]), the bias voltage, the layout, the bipolar amplification, the shallow trench isolation (STI) and the fabrication process. In the case of this work, the low substrate coupling effect induced by the bulk FinFET technology is taking into account at electrical level.…”
Section: See Prediction Toolmentioning
confidence: 99%
“…Particularly in sub-micron technologies, charge sharing effects have been observed in digital [4], [19] and analog [12], [13], [15], [20] circuits. This can cause multiple errors by a single ion strike or even pulse quenching in ion-induced transients, resulting in a reduced overall sensitivity of the system against SEE [12], [13], [15], [20], [21].…”
Section: Analogmentioning
confidence: 99%
“…Given the fact that transistors of the differential stage were laid out to maximize device matching, it is logical to consider charge sharing effects as observed in digital [4], [6], [19], [41], [42] and analog circuits [20], [43], [44] built in sub-micron technologies. In fact, charge sharing has been proposed as a mechanism to desensitize sections of analog circuits and evaluated through laser experiments [10], [12], [13], [45].…”
Section: A Experimental Observation Of Charge Sharingmentioning
confidence: 99%
“…This design specificity impacts the drive current of the floating nodes of the DFF. The floating nodes are known as potential critical areas for the occurrence of SEU in digital devices [3], [10], [11]. Fig.…”
Section: A Architecture and Design Dependence Of The Seu Sensitivitymentioning
confidence: 99%