Pulse shrinkage based pre-bond through silicon vias test in 3D IC

Abstract

Defects in TSV not only lead to variation in the propagation delay but also in the transition delay of the net connected to the TSV. A non-invasive approach for pre-bond TSV test based on pulse shrinkage is proposed to detect resistive open and leakage fault. TSVs are used as capacitive loads of their driving gates, then the pulse visiting the cyclic shrinkage cells will be shrunk until it vanishes completely. The shrinkage amount is digitized into a digital code to compare with an expected value of fault free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of resistive open defects 0.2kΩ above and equivalent leakage resistance less than 40M Ω. The estimated design for testability area cost of our method is negligible for realistic dies. IEEE 33rd VLSI Test Symposium (VTS)978-1-4799-7597-6/15/$31.00 ©2015 IEEE

Vernier ring based pre-bond through silicon vias test in 3D ICs

“…For simplicity without losing generality, a lumped RC model to represent a TSV has been widely presented in previous works [4], where R is the TSV resistance and C is the parasitic capacitance between the TSV and the substrate. R is generally neglected in the pre-bond phase, and a simplified model is considered (see Fig.…”

“…To overcome this problem, Liang et al [4] proposed a technique named pulse shrinkage (PS), which can generate digital codes to manifest the faulty degrees. In this scheme, a pulse becomes the input signal, and there are several shrinkage cells in the test path.…”

“…Mechanical force on TSV tips and micro-bumps can result in damage to TSVs, leading to their degraded performance or even failure. As an alternative to probe testing, built-in self-test (BIST) approaches have been developed [3,4,5,6,7].…”

An enhanced time-to-digital conversion solution for pre-bond TSV dual faults testing

“…Testing for manufacturing defects is inherently important to ensure the required product quality since one single defect in a TSV may damage the entire 3D IC. Hence, TSVs need to be thoroughly tested to enhance their yield and reliability [2,3,4,5,6]. Pre-bond TSV testing is always one of the main challenges in 3D-IC test flow due to the limited TSV accessibility.…”

“…In [6], we have illustrated a pulse shrinkage method for pre-bond TSV testing, it can detect TSV faults with high resolution. However, when the resistive open fault occurs, the change of pulse width caused by open circuit fault is very small or even negligible.…”