Single-event transient (SET) induced harmonic errors have been observed in digitally controlled ring oscillators (DCRO). Accumulated phase error is used to characterize harmonic errors in ring oscillator circuits. An analytical model for determining minimum and maximum SET transient duration capable of generating a harmonic is described. Simulation and TPA laser experimental results on a 40-nm DCRO are shown to confirm the assertion of the harmonic vulnerability window with respect to SET pulsewidth. Further more, fault injection experimental results on three RO designs built with discrete commercial off-the-shelf components are included to demonstrate the relationship between harmonic response and SET pulsewidth. Index Terms-ADPLL, DCO, digital circuits, harmonic error, ring oscillator, single-event transient (SET).