Putting routing tables in silicon

Pei, T.-B.; Zukowski, C.

doi:10.1109/65.120723

Cited by 71 publications

(15 citation statements)

References 9 publications

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“…The reason is the removal of the prioritizer circuit from critical path of the RCAM architecture. Analytically, the overall search time of RCAM architecture is given by: t rcam search 2t rcam block + t encoder (5) where, t rcam block is the delay of the RCAM block (n × w cells) and t encoder is the delay of a regular n-input encoder logic. The analytical expression for the overall search time of a conventional TCAM architecture is given by: t tcam search t tcam block + t priority encoder (6) where, t tcam block is the delay of the TCAM block (n × w cells) and t priority encoder is the delay of a n-input priority encoder logic.…”

Section: A Search Timementioning

confidence: 99%

A Reconfigurable CAM Architecture for Network Search Engines

Nourani

Vijayasarathi

Balsara

2006

2006 International Conference on Computer Design

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Section: A Search Timementioning

confidence: 99%

A Reconfigurable CAM Architecture for Network Search Engines

Nourani

Vijayasarathi

Balsara

2006

2006 International Conference on Computer Design

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“…Hardware route lookup and forwarding is also under active investigation in both research and commercial designs [30,31]. The argument for a software-based implementation stresses¯exibility.…”

Section: Route Lookupmentioning

confidence: 99%

On the design of IP routers Part 1: Router architectures

Aweya

2000

Journal of Systems Architecture

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Internet Protocol (IP) networks are currently undergoing transitions that mandate greater bandwidths and the need to prepare the network infrastructures for converged trac (voice, video, and data). Thus, in the emerging environment of high performance IP networks, it is expected that local and campus area backbones, enterprise networks, and Internet Service Providers (ISPs) will use multigigabit and terabit networking technologies where IP routers will be used not only to interconnect backbone segments but also to act as points of attachments to high performance wide area links. Special attention must be given to new powerful architectures for routers in order to play that demanding role. In this paper, we describe the evolution of IP router architectures and highlight some of the performance issues aecting IP routers. We identify important trends in router design and outline some design issues facing the next generation of routers. It is also observed that the achievement of high throughput IP routers is possible if the critical tasks are identi®ed and special purpose modules are properly tailored to perform them. Ó

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“…In addition to the algorithmic and software approaches on LUT search, some researchers offered hardware solutions. For example, [12] proposes hardware implementation of tries of high radix for exact matching and [13] uses internal SRAMs for the entire routing table. Also, using content-addressable memory (CAM) and utilizing the cache are proposed in [14] and [13], respectively.…”

Section: A Prior Work and Main Contributionmentioning

confidence: 99%