Q-Function-Based Traffic- and Thermal-Aware Adaptive Routing for 3D Network-on-Chip

Lee, Seung Chan; Han, Tae Hee

doi:10.3390/electronics9030392

Cited by 15 publications

(8 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…has good potential to increase beneficial NoC performance, and power dissipation, as outlined in the studies [60][61][62][63][64]. In [60 58], depending on traffic-flow, the 2D mesh was examined using ANN to detect the hotspots.…”

Section: On-chip Network Developmentsmentioning

confidence: 99%

“…However, that model was constrained because of latency issuance, due to specific injection rate values. The research [63] applied the Q-reinforcement methodology to a thermally aware adaptive routing protocol, with the aim of predicting the routing, based on the routers' thermal activity. With the Q-table scale, this design was challenging, as the numerical mechanism was inefficient with all NoC tiles, and a larger NoC scale, which in turn resulted in higher costs.…”

Section: On-chip Network Developmentsmentioning

confidence: 99%

See 1 more Smart Citation

Power-aware Future Computing Systems Using Machine Learning Techniques

Al-Obaidy

2024

Preprint

View full text Add to dashboard Cite

<p>There is a growing demand for hardware systems that are computationally efficient and energy saving, to accelerate compute-intensive applications. These exciting challenges, such as memory access and GPU throughput, take performance, power, and resource trade-offs into account. This is especially relevant to a relatively new approach: Accelerating and running parallel computing systems using a machine learning (ML) technique. The objective of this thesis is to explore the hardware design requirements, and select appropriate choices for multi-core architectures, based on different ML, to address these challenges. This thesis contributes by developing effective hardware architectures which trade-off design objectives, by focusing on the following four distinct fields: • Utilization of low-power cache designs. The objective of this design is to use the artificial neural network (ANN) predictive model to optimize a hybrid spin-torque transfer random-access memory (STT-RAM), and static random-access memory (SRAM), for multicore chips. The simulation results demonstrate that the approach can result in significant power-aware improvement for different workloads. • Development of algorithms that facilitate power savings for three-dimensional integrated networks-on-chips (3D-NoCs) design. A novel approach was efficiently developed to predict the suitable routing algorithm based on the ANN model. A trade-off power-performance function was extracted as a target for the prediction mechanism. The obtained results show high throughput with low power consumption, and reduced thermal hotspots. • Enhance power-aware resources for general purpose graphics processing unit (GPGPU). The customized model is obtained by utilizing the available chip units for each application. The energy-delay product was adopted as the target factor for the proposed ANN model. The results show that when the GPU platform is tuned to the required resources, prediction accuracy, and power consumption are highly improved. This methodology provides more flexibility for the running application to face power challenges when using maximum hardware on the GPU systems. • To improve the performance of the 3D-NoC accelerator platform, we extended the integrated 3D-NoC based ANN simulator to support interconnection routing through adding torus topology. The simulation results for the case study concluded that the modified platform contributes towards low latency and reduced power consumption, especially with respect to high NoC dimensions.</p>

show abstract

Section: On-chip Network Developmentsmentioning

confidence: 99%

Section: On-chip Network Developmentsmentioning

confidence: 99%

Power-aware Future Computing Systems Using Machine Learning Techniques

Al-Obaidy

2024

Preprint

View full text Add to dashboard Cite

show abstract

“…An agent learns from its own action during system activity in a simulation environment. The reward values for agents are recorded and updated in the table located in the router also known as Q- To improve overall node utilization Q-learning based adaptive routing is presented in [18], focusing on balancing inter-layer traffic distribution. It also offers an extensive congestion investigation to reduce performance degradation.…”

Section: Related Workmentioning

confidence: 99%

Interval Based Transaction Record Keeping Mechanism for Adaptive 3D Network-on-Chip Routing

2022

IJIES

View full text Add to dashboard Cite

Due to technology scaling, network-on-chip (NoC) become the viable solution for on-chip many-core systems. The most critical concern of NoC is congestion management caused due to heavy communication traffic between nodes. Without an appropriate congestion resolution strategy for reducing heavy in-network traffic, the efficiency of the entire network is damaged severely. In this paper, an interval based record-keeping mechanism is presented to reduce network traffic and congestion by maintaining a history table and previous packet transaction records at each node. Proposed method performs certain validity checks before allowing using previous transaction record from history table. The performance of the technique is investigated in terms of average delay and compared to the state-of-the-art routing algorithms using the Access Noxim simulator. The simulation results demonstrate that the proposed method has outperformed in terms of global average delay, with 8-12% improvement, the average number of hits is 26-61% greater than misses under different synthetic traffic. The proposed algorithm has been tested under various topological configurations for efficiency evaluations.

show abstract

“…QTTAR [17] is a Q-learning-based adaptive 3D routing algorithm that improves overall node utilization by balancing inter-layer traffic distribution and offering a more precise congestion analysis to prevent RTM-related performance degradations. By balancing the distribution of overheated regions in a layer, QTTAR reduces differences in inter-layer cooling performance.…”

Section: Literature Reviewmentioning

confidence: 99%

Thermal-aware Dynamic Weighted Adaptive Routing Algorithm for 3D Network-on-Chip

Kaleem¹,

Isnin²

2021

IJACSA

View full text Add to dashboard Cite

Network-on-Chip NoC based systems have severe thermal problems due to the stacking of dies and disproportionate cooling efficiency of different layers. While adaptive routing can help with thermal issues, current routing algorithms are either thermally imbalanced or suffer from traffic congestion. In this work a novel thermal aware dynamic weighted adaptive routing algorithm has been proposed that takes traffic and temperature information into account and prevents packets being routed across congested and thermally aggravated areas. Dynamic weighted model will consider parameters related to congestion and thermal issues and provide a balanced suitable approach according to the current scenario at each node. The efficiency of the proposed algorithm is analyzed and evaluated with state-of-the-art thermal-aware routing algorithms using a simulation environment. Results obtained from the simulation shows that the proposed algorithm has performed better in terms of global average delay with 17-33 percent improvement and better thermal profiling under various synthetic traffic conditions.

show abstract

Q-Function-Based Traffic- and Thermal-Aware Adaptive Routing for 3D Network-on-Chip

Cited by 15 publications

References 26 publications

Power-aware Future Computing Systems Using Machine Learning Techniques

Power-aware Future Computing Systems Using Machine Learning Techniques

Interval Based Transaction Record Keeping Mechanism for Adaptive 3D Network-on-Chip Routing

Thermal-aware Dynamic Weighted Adaptive Routing Algorithm for 3D Network-on-Chip

Contact Info

Product

Resources

About