Q-modules: internally clocked delay-insensitive modules

Abstract

Q-modules are internally-clocked modules that can be used to satisfy delay-insensitive specifications. The allowed changes of inputs to, and outputs from, a delay-insensitive module are specified by partial orderings of these signals in such a way that the set of possible behaviors remains unchanged with arbitrary values of delay inserted in series with each input and output path. A two-phase single-wire clock and a single-wire clock acknowledge are used for sequence control and accommodate any value of flip-flop hold time. The clock distribution within a Qmodule is also delay insensitive and the modules will operate correctly with any value of delay inserted in series with the clock distribution. Metastable flip-flop operation due to input signal changes will not cause failures hut will only extend the clock cycle time. Correct sequence operation is ensured in exchange for an occasional clock cycle extension. The only delay constraint that must be satisfied in assembling a Q-module from its predesigned components is a one-sided requirement that a particular clock phase be longer than the longest delay through the combinational logic of the module. Prototypes of components to implement Qmodules have been designed, and a design aid program, QSYN, to place instances of these components, personalize a PLA, and generate a MAGIC or CIF file for a CMOS realization, including the delay circuitry, is being developed. Testability is one of the advantages of Q-modules over clock-free delay-insensitive modules; circuitry is included in the cells for testing the logic and interconnections.

A Methodology for Correct-by-Construction Latency Insensitive Design

“…In particular, the idea of a design methodology which is inherently modular is already present in the work on Macromodular Computer Systems by Clark and Molnar [5,6]. To separate the design of these modules by the design of the system and make the entire process amenable to automation, the modules must be implemented as delay-insensitive circuits [24,26]. A delay-insensitive circuit is designed to operate correctly regardless of the delays on its gates and wires (unbounded delay model) [32].…”

“…To be able to build complex systems one must use more complex components, which are "externally" delay insensitive, while "internally" are designed by carefully verifying their timing and avoiding or tolerating metastability [13,17,26]. By slightly relaxing the unbounded delay model and allowing "isochronic forks" 2 , practical quasi-delay-insensitive circuits can be built using simple logic gates [3].…”

Theory of latency-insensitive design

“…In particular, the idea of a design methodology which is inherently modular is already present in the work by Clark and Molnar [17], [18]. To separate the design of these modules from the design of the system and make the entire process amenable to automation, the modules must be implemented as delay-insensitive circuits [19], [20]. A delay-insensitive circuit is designed to operate correctly regardless of the delays on its gates and wires (unbounded delay model) [21].…”

Asynchronous design methodologies: an overview

“…The second implementation strategy [22,27] is similar to the locally-clocked burst-mode circuits discussed earlier. However, instead of generating a clock only when inputs arrive, a locally-clocked module (Q-module ) is constantly clocking its latches.…”