Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs

Yan, Aibin; Ling, Yafei; Cui, Jie; Chen, Zhili; Huang, Zhengfeng; Song, Jie; Girard, Patrick; Wen, Xiaoqing

doi:10.1109/tcsi.2019.2959007

Cited by 38 publications

(14 citation statements)

References 27 publications

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“…For fair comparisons, the CLCT [3 ], the DIRT [4 ], the Delta‐DICE [5 ] and the DNUCT [6 ] latches were designed in the same technology. Table 1 presents performance comparisons of five latches with respect to silicon area, power dissipation (defined as the average value of dynamic and static power dissipation), delay (defined as the maximum delay of D rise and fall propagating from D to Q) and APDP (calculated by multiplying area, power and delay).…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Nevertheless, what is worse, soft error from SEDU induced by charge collection and charge sharing in multiple nodes are ascending [2] as a consequence of increasingly shrinking process feature size. On this occasion, some SEDU-tolerant latches [3][4][5][6] have been presented to deal with this kind of problem. Unfortunately, in terms of actual application, these latches are facing plenty of overhead of area, power dissipation and propagation delay.…”

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confidence: 99%

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High‐performance and single event double‐upset‐immune latch design

et al. 2020

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This Letter proposes a single event double-upset (SEDU)-fully-tolerant latch, referred to as FBSET, mainly featuring four interlocked branch circuits implemented by stacking three PMOS and one NMOS transistors or three NMOS and one PMOS transistors to achieve low power dissipation. The latch exhibits up to 84.56% area-power-delay product saving compared with recently reported latches. Simulation results validate that the proposed latch is completely immune to SEDU.

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Section: Simulation Resultsmentioning

confidence: 99%

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confidence: 99%

High‐performance and single event double‐upset‐immune latch design

et al. 2020

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“…The probability of the multiple node upset is gradually increasing. Due to the better performance and lower overhead of this structure, multiple-node upset-tolerant latches can be designed with this structure in future work [40].…”

Section: Discussionmentioning

confidence: 99%

LIHL: Design of a Novel Loop Interlocked Hardened Latch

Liu

Yu³

et al. 2021

Electronics

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A single event causing a double-node upset is likely to occur in nanometric complementary metal-oxide-semiconductor (CMOS). Contemporary hardened latch designs are insufficient in meeting high reliability, low power consumption, and low delay. This paper presents a novel soft error hardened latch, known as a loop interlocked hardened latch (LIHL). This latch consists of four modified cross-coupled elements, based on dual interlocked storage cell (DICE) latch. The use of these elements hardens the proposed LIHL to soft errors. The simulation results showed that the LIHL has single-event double upset (SEDU) self-recoverability and single-event transient (SET) pulse filterability. This latch also reduces power dissipation and propagation delay, compared to other SEDU or SET-tolerant latches.

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“…single-node upsets (SNUs), double-node upsets (DNUs), and even triple-node upsets (TNUs) [1]. Soft errors are transient errors, meaning that the affected circuit is not physically damaged and the errors can be eliminated by data reloading or on-line self-recovering through the radiation-hardening-by-design (RHBD) approach.…”

mentioning

confidence: 99%

“…This is because, under charge-sharing mechanisms, the logic state of adjacent circuit nodes are becoming more and more easily disturbed by high-energy-particle striking [2][3]. Therefore, not only SNUs and DNUs but also TNUs should be considered for radiation hardening in advanced safety-critical nano-scale circuits, such as memory cells [3][4][5][6], flip-flops [7][8][9], and latch designs [1][2][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27].…”

mentioning

confidence: 99%

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

Yan

Zhou

et al. 2021

Microelectronics Journal

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This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.

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Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs

Cited by 38 publications

References 27 publications

High‐performance and single event double‐upset‐immune latch design

High‐performance and single event double‐upset‐immune latch design

LIHL: Design of a Novel Loop Interlocked Hardened Latch

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

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