Quantification of Shallow-junction Dopant Loss during CMOS Process

Abstract

We analyzed dopant concentration and profiles in source drain extension (SDE) by using in-line low energy electron induced x-ray emission spectrometry (LEXES), four point probe (FPP), and secondary ion mass spectroscopy (SIMS). By monitoring the dopant dose with LEXES, dopant loss in implantation and annealing process was successfully quantified. To measure the actual SDE sheet resistance in CMOS device structure without probe penetration in FPP, we fabricated a simple SDE sheet-resistance test structure (SSTS) by modifying a conventional CMOS process. It was found that the sheet resistances determined with SSTS are larger than those measured with FPP. There are three mechanisms of dopants loss in CMOS process: 1) wet-etching removal during photo resist cleaning, 2) out-diffusion, and 3) deactivation by post-thermal process. We quantified the loss of the dopant in SDE during the CMOS process, and found that the wet-etching removal and out-diffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively.

Quantitative analysis of ultrashallow junction of sub-50nm gate-length transistors: Junction depth, sheet resistance, short channel effects, and transistor performance

“…5 Since most of the USJ dopant resides near surface, the outdiffusion results in considerable underestimation of RTA activation level especially for shallower implantation. 5 Since most of the USJ dopant resides near surface, the outdiffusion results in considerable underestimation of RTA activation level especially for shallower implantation.…”

“…5 Since most of the USJ dopant resides near surface, the outdiffusion results in considerable underestimation of RTA activation level especially for shallower implantation. 5 If we define junction depth as the position of boron concentration of 5 ϫ 10 18 /cm 3 , junction depth does not change much by the formation of spacer oxide and SiN, but significant boron outdiffusion into the spacer is found. To measure the dopant loss into the spacer, we measured SIMS profile at each step: ͑1͒ as-implantation with BF 2 with the dose of 2 ϫ 10 15 /cm 2 and the energy of 2 keV, ͑2͒ spacer oxide formation ͑800°C, 1 min͒, ͑3͒ spacer SiN formation ͑600°C, 1 h͒, and ͑4͒ spike RTA ͑peak temperature of 1050°C͒.…”

“…1 The requirement becomes more and more rigorous as the device is scaled into sub-50 nm scale, and is simply not achievable with standard technology due to solid-solubility limitations and sheet resistance ͑R S ͒ rise as junction depth ͑X J ͒ drops. 5 Moreover, for such shallow junction, the dopant loss and carrier deactivation in the CMOS process should be strictly controlled to maintain the high doping level. Although these technologies have been proven to give distinguishable improvements in the R S / X J graph, the performance gain after device integration is relatively poor.…”