We analyzed dopant concentration and profiles in source drain extension (SDE) by using in-line low energy electron induced x-ray emission spectrometry (LEXES), four point probe (FPP), and secondary ion mass spectroscopy (SIMS). By monitoring the dopant dose with LEXES, dopant loss in implantation and annealing process was successfully quantified. To measure the actual SDE sheet resistance in CMOS device structure without probe penetration in FPP, we fabricated a simple SDE sheet-resistance test structure (SSTS) by modifying a conventional CMOS process. It was found that the sheet resistances determined with SSTS are larger than those measured with FPP. There are three mechanisms of dopants loss in CMOS process: 1) wet-etching removal during photo resist cleaning, 2) out-diffusion, and 3) deactivation by post-thermal process. We quantified the loss of the dopant in SDE during the CMOS process, and found that the wet-etching removal and out-diffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively.

Articles you may be interested inComparison of two surface preparations used in the homoepitaxial growth of silicon films by plasma enhanced chemical vapor deposition J. Vac. Sci. Technol. B 21, 970 (2003); 10.1116/1.1568352 Effect of Si cap layer on parasitic channel operation in Si/SiGe metal-oxide-semiconductor structures J. Appl. Phys. 93, 3545 (2003); 10.1063/1.1542916Two-dimensional dopant concentration profiles from ultrashallow junction metal-oxide-semiconductor field-effect transistors using the etch/transmission electron microscopy methodThe loss of the dopant in ultrashallow junction ͑USJ͒ by RCA standard clean ͑SC1͒ prior to the formation of side-wall spacer is quantified by using transmission electron microscopy ͑TEM͒, secondary ion mass spectroscopy, four-point probe, and source/drain extension ͑SDE͒ sheet-resistance test structure ͑SSTS͒. From the cross-sectional TEM images, the etched depth by one SC1 for n ͑p͒-type SDE was measured to be 1.5 nm ͑0.2 nm͒. From the secondary ion mass spectroscopy profiles, most of the n-type dopant implanted with arsenic at 2 keV is expected to be etched-out by four times of SC1 cleaning, while the p-type dopants are immune to SC1 cleaning. We quantified the dopant loss from sheet resistance measurements with the four-point probe and the SSTS. The effect of SC1 cleaning on transistor performance is discussed in terms of on-state current. The dopant loss by SC1 is found to be the most significant factor in process optimization for n-type field effect transistor with USJ.

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Articles you may be interested inDopant profiling in vertical ultrathin channels of double-gate metal-oxide-semiconductor field-effect transistors by using scanning nonlinear dielectric microscopy Appl. Phys. Lett. 85, 4139 (2004); 10.1063/1.1812571 Secondary ion mass spectrometry characterization of source/drain junctions for strained silicon channel metal-oxide-semiconductor field-effect transistors Two-dimensional ultrashallow junction characterization of metal-oxide-semiconductor field effect transistors with strained silicon Two-dimensional dopant concentration profiles from ultrashallow junction metal-oxide-semiconductor field-effect transistors using the etch/transmission electron microscopy method Shallow junctions diffused from single-and coimplanted WSi 2 films and integrated 0.2 μm complementary metal-oxide-semiconductor transistorsWe analyzed causes of dopant loss in ultrashallow junction during complementary metal-oxide-semiconductor ͑CMOS͒ fabrication: ͑1͒ sputtering-out during ion implantation, ͑2͒ wet-etching removal in cleaning process, ͑3͒ outdiffusion, and ͑4͒ deactivation in post-thermal process. By using low energy electron induced x-ray emission spectrometry and other conventional analytic techniques such as four-point probe ͑FPP͒ and SIMS, the dopant losses are quantified. We developed a simple source/drain extension ͑SDE͒ sheet-resistance test structure to measure the actual sheet resistance of SDE to avoid sizable error due to FPP probe penetration. By comparing with CMOS electrical data, practical aspect of junction depth and sheet resistance is discussed in terms of short channel effects and on-state current. It is found that deactivation and wet-etching removal of arsenic dopant during cleaning process are the major factors in scaling of n-type transistor, while junction depth is the major one in scaling of p-type transistor.

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