Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design

Wong, Henry; Betz, Vaughn; Rose, Jonathan

doi:10.1109/tvlsi.2013.2284281

Cited by 13 publications

(6 citation statements)

References 53 publications

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“…The CAM circuits, described above, face several design tradeoffs that have limited their use in many microarchitectural components [16], [26], [65], instead giving preference to alternative implementations based on SRAM or register files [66]. These tradeoffs and challenges, including speed, energy consumption, scalability, and area overhead, are elaborated upon hereafter.…”

Section: B Tradeoffs and Challenges In Cam Designmentioning

confidence: 99%

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture

Garzón,

Hanhan,

Lanuzza

et al. 2024

IEEE Access

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Associative access is widely used in fundamental microarchitectural components, such as caches and TLBs. However, associative (or content addressable) memories (CAMs) have been traditionally considered too large, too energy-hungry, and not scalable, and therefore, have limited use in modern computer microarchitecture. This work revisits these presumptions and proposes an energy-efficient fullyassociative tag array (FASTA) architecture, based on a novel complementary CAM (CCAM) bitcell. CCAM offers a full CMOS solution for CAM, removing the need for time-and energy-consuming precharge and combining the speed of NOR CAM and low energy consumption of NAND CAM. While providing better performance and energy consumption, CCAM features a larger area compared to state-of-the-art CAM designs. We further show how FASTA can be used to construct a novel aliasing-free, energy-efficient, Very-Many-Way Associative (VMWA) cache. Circuit-level simulations using 16 nm FinFET technology show that a 128 kB FASTA-based 256-way 8-set associative cache is 28% faster and consumes 88% less energy-per-access than a same sized 8-way (256-set) SRAM based cache, while also providing aliasingfree operation. System-level evaluation performed on the Sniper simulator shows that the VMWA cache exhibits lower Misses Per Kilo Instructions (MPKI) for the majority of benchmarks. Specifically, the 256way associative cache achieves 17.3%, 11.5%, and 1.2% lower average MPKI for L1, L2, and L3 caches, respectively, compared to a 16-way associative cache. The average IPC improvement for L1, L2, and L3 caches are 1.6%, 1.4%, and 0.2%, respectively.

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Section: B Tradeoffs and Challenges In Cam Designmentioning

confidence: 99%

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture

Garzón,

Hanhan,

Lanuzza

et al. 2024

IEEE Access

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“…ASIC multi-ported RAMs are a classic culprit of poor resource utilization in FPGA prototypes, as they cannot be trivially implemented in BRAM and are instead decomposed into LUTs and registers [27]. While using double-pumping, BRAM duplication, or FPGA-optimized microarchitectures [17] can help, Golden Gate can automatically substitute a decoupled model to further reduce resource utilization.…”

Section: Case Study: Multi-ported Memoriesmentioning

confidence: 99%

“…(1) Other Resource Optimizations. CAMs are another FPGA-hostile structure [27] that can be replaced with multi-cycle models.…”

Section: Future Workmentioning

confidence: 99%

“…We also contribute lime, a push-button checker that verifies that an optimized model simulates its ASIC source exactly. Finally, we perform a case study, where Golden Gate and lime are used to time-multiplex highly ported memories, optimizing a traditionally FPGA-hostile element of ASIC designs [27]. This enables us to emulate a large RISC-V multiprocessor SoC on a single FPGA, where a partitioned prototype would otherwise have been required.…”

Section: Introductionmentioning

confidence: 99%

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Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes

Magyar

Biancolin

Koenig

et al. 2019

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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We present Golden Gate, an FPGA-based simulation tool that decouples the timing of an FPGA host platform from that of the target RTL design. In contrast to previous work in static time-multiplexing of FPGA resources, Golden Gate employs the Latency-Insensitive Bounded Dataflow Network (LI-BDN) formalism to decompose the simulator into subcomponents, each of which may be independently and automatically optimized. This structure allows Golden Gate to support a broad class of optimizations that improve resource utilization by implementing FPGA-hostile structures over multiple cycles, while the LI-BDN formalism ensures that the simulator still produces bit-and cycle-exact results. To verify that these optimizations are implemented correctly, we also present lime, a model-checking tool that provides a push-button flow for checking whether optimized subcomponents adhere to an associated correctness specification, while also guaranteeing forward progress. Finally, we use Golden Gate to generate a cycle-exact simulator of a multi-core SoC, where we reduce LUT utilization by up to 26% by coercing multi-ported, combinationally read memories into simulation models backed by time-multiplexed block RAMs, enabling us to simulate 50% more cores on a single FPGA.

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“…(2) FPGA Capacity. Common ASIC structures, such as CAMs and multi-ported RAMs, map poorly to FPGA fabrics [24], making it difficult to host large ASIC designs on FPGAs. (3) Ease of Use.…”

Section: Adoption Challengesmentioning

confidence: 99%

Fased

Biancolin

Karandikar

Kim

et al. 2019

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Recent work in FPGA-accelerated simulation of ASICs has shown that much of a simulator can be automatically generated from ASIC RTL. Alas, these works rely on simple models of the outer cache hierarchy and DRAM, as mapping ASIC RTL for these components into an FPGA fabric is too complex and resource intensive. To improve FPGA simulation model accuracy, we present fased, a parameterized generator of composable, high-fidelity, FPGA-hosted last-level-cache and DRAM models. fased instances are highly performant, yet they maintain timing faithfulness independently of the behavior of the host-FPGA memory system. For a given scheduling policy, a single fased instance can model nearly the entire space of realizable single-channel DDR3 memory organizations, without resynthesizing the simulator RTL. We demonstrate fased by integrating it into a flow that automatically transforms RTL for multicore RISC-V processors into full-system simulators that execute at up to 150 target MHz on cloud-hosted FPGAs.

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Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design

Cited by 13 publications

References 53 publications

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture

Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes

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