Quantitative analysis of charge trapping and classification of sub-gap states in MoS₂ TFT by pulse I–V method

Abstract

The threshold voltage instabilities and huge hysteresis of MoS thin film transistors (TFTs) have raised concerns about their practical applicability in next-generation switching devices. These behaviors are associated with charge trapping, which stems from tunneling to the adjacent trap site, interfacial redox reaction and interface and/or bulk trap states. In this report, we present quantitative analysis on the electron charge trapping mechanism of MoS TFT by fast pulse I-V method and the space charge limited current (SCLC) measurement. By adopting the fast pulse I-V method, we were able to obtain effective mobility. In addition, the origin of the trap states was identified by disassembling the sub-gap states into interface trap and bulk trap states by simple extraction analysis. These measurement methods and analyses enable not only quantitative extraction of various traps but also an understanding of the charge transport mechanism in MoS TFTs. The fast I-V data and SCLC data obtained under various measurement temperatures and ambient show that electron transport to neighboring trap sites by tunneling is the main charge trapping mechanism in thin-MoS TFTs. This implies that interfacial traps account for most of the total sub-gap states while the bulk trap contribution is negligible, at approximately 0.40% and 0.26% in air and vacuum ambient, respectively. Thus, control of the interface trap states is crucial to further improve the performance of devices with thin channels.

A comparative study of charge trapping effect in p-type MoTe2 and WSe2 FETs using pulsed current–voltage measurements

“…where μ fast is the extracted mobility from the single-pulse measurement. 23,31) Figure 6(b) compares the extracted…”

“…[16][17][18][19] Although surface passivation or electrical characterization in vacuum are recommended to minimize the surface trapping effect, pulsed measurements have been proposed as a simple and reliable method to evaluate intrinsic properties of 2D semiconductors. [20][21][22][23] However, limited studies were reported on pulsed I-V study of p-type 2D FETs.…”

High voltage endurance and switchable resistance effect observed in nanoscale copper groove structure

“…It means that the conduction properties of this structure can flexibly switch between high resistance property and low resistance property. We analyzed the electric transport process in this structure and attribute this switchable effect to the change of Schottky barrier caused by the charge trapping effect [21][22][23][24][25][26]. This work may help develop a new approach for the design of resistance devices and provide the incentive for the development of laser-and pulse-modulated photoelectric devices.…”

Investigation of interface properties of h-BN and AlN on AlGaN/GaN heterostructures

“…The quality of interface between gate insulator and the GaN cap layer is crucial for the AlGaN/GaN MISHEMTs to achieve excellent and reliable performance. For example, in switching applications it is important to investigate the interface traps as they could degrade device switching properties through the charging and discharging phenomenon [90]. Many characterization techniques have been developed to evaluate the interfacial quality.…”

“…The quality of interface between gate insulator and the semiconductor wafer is crucial for the AlGaN/GaN MISHEMTs to achieve excellent and reliable performance. For example, in switching applications it is important to investigate the interface traps as they could degrade device switching properties through charging and discharging [90]. Although researchers have realized MISHEMTs with h-BN, [91]- [93] no interface properties have so far been reported for VO h-BN on AlGaN/GaN heterostructures.…”