Quantitative Analysis of the Density of Trap States in Semiconductors by Electrical Transport Measurements on Low-Voltage Field-Effect Transistors

Geiger, Michael; Schwarz, Lukas; Zschieschang, Ute; Manske, Dirk; Pflaum, Jens; Weis, J.; Klauk, Hagen; Weitz, R. Thomas

doi:10.1103/physrevapplied.10.044023

Cited by 30 publications

(29 citation statements)

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“…The trap densities of D18:BTPR:Y6 ternary BHJ thin film with an energy depth of 0.1–0.15 eV are as low as around 3–6 × 10 15 cm −3 , which is quite consistent with that measured from SCLC method, and much lower than those values (10 16 to 10 18 cm −3 ) [ 51 ] reported for thin film of organic semiconductors. [ 41,51,53 ] In addition, this low trap density of D18:Y6 with BTPR additives is comparable to and even lower than those of some typical high‐performance inorganic/hybrid semiconductors, such as (10 16 cm −3 ) amorphous silicon, [ 42 ] (10 16 cm −3 ) metal oxides, [ 41 ] and (10 14 to 10 15 cm −3 ) halide perovskite thin film. [ 30 ] According to the analysis of the relationship between trap density and device efficiency in the literature, [ 30 ] solar cells given with around 10 15 cm −3 magnitude of trap densities, have capacity to obtain a PCE of up to 20%.…”

Section: Resultsmentioning

confidence: 93%

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An Electron Acceptor Analogue for Lowering Trap Density in Organic Solar Cells

et al. 2021

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Typical organic semiconductor materials exhibit a high trap density of states, ranging from 1016 to 1018 cm−3, which is one of the important factors in limiting the improvement of power conversion efficiencies (PCEs) of organic solar cells (OSCs). In order to reduce the trap density within OSCs, a new strategy to design and synthesize an electron acceptor analogue, BTPR, is developed, which is introduced into OSCs as a third component to enhance the molecular packing order of electron acceptor with and without blending a polymer donor. Finally, the as‐cast ternary OSC devices employing BTPR show a notable PCE of 17.8%, with a low trap density (1015 cm−3) and a low energy loss (0.217 eV) caused by non‐radiative recombination. This PCE is among the highest values for single‐junction OSCs. The trap density of OSCs with the BTPR additives, as low as 1015 cm−3, is comparable to and even lower than those of several typical high‐performance inorganic/hybrid counterparts, like 1016 cm−3 for amorphous silicon, 1016 cm−3 for metal oxides, and 1014 to 1015 cm−3 for halide perovskite thin film, and makes it promising for OSCs to obtain a PCE of up to 20%.

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Section: Resultsmentioning

confidence: 93%

“…The trap density of OSCs employing BTPR additives as low as 10 15 cm −3 is comparable to and even lower than those of amorphous silicon and some other high-performance inorganic/hybrid counterparts. [30,41,42] The trap density of around 10 15 cm −3 is the precondition for OSCs with a 20% PCE.…”

Section: Introductionmentioning

confidence: 99%

An Electron Acceptor Analogue for Lowering Trap Density in Organic Solar Cells

et al. 2021

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“…We have applied the extended Grünewald method to extract the density of trap states (trap DOS) in the organic‐semiconductor layer from the measured transfer curves of the TFTs in the linear regime of operation. [ 39 ] We were able to apply this method only to the TFTs on the five smoothest substrates, since the TFTs on the three rougher substrates do not meet the criteria for a meaningful extraction of the trap DOS from the transfer curves of the TFTs. The results are summarized in Figure 3b where the trap DOS in the semiconductor is plotted as a function of the energy relative to the valence‐band edge for the five smoothest substrates.…”

Section: Resultsmentioning

confidence: 99%

Effect of the Degree of the Gate‐Dielectric Surface Roughness on the Performance of Bottom‐Gate Organic Thin‐Film Transistors

Geiger

Acharya

Reutter

et al. 2020

Adv Materials Inter

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In organic thin‐film transistors (TFTs) fabricated in the inverted (bottom‐gate) device structure, the surface roughness of the gate dielectric onto which the organic‐semiconductor layer is deposited is expected to have a significant effect on the TFT characteristics. To quantitatively evaluate this effect, a method to tune the surface roughness of a gate dielectric consisting of a thin layer of aluminum oxide and an alkylphosphonic acid self‐assembled monolayer over a wide range by controlling a single process parameter, namely the substrate temperature during the deposition of the aluminum gate electrodes, is developed. All other process parameters remain constant in the experiments, so that any differences observed in the TFT performance can be confidently ascribed to effects related to the difference in the gate‐dielectric surface roughness. It is found that an increase in surface roughness leads to a significant decrease in the effective charge‐carrier mobility and an increase in the subthreshold swing. It is shown that a larger gate‐dielectric surface roughness leads to a larger density of grain boundaries in the semiconductor layer, which in turn produces a larger density of localized trap states in the semiconductor.

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“…In particular, n-type organic semiconductors are prone to degradation if they are exposed even to the smallest concentrations of oxygen and water. Additionally, due to the low temperature of the substrate during processing (room temperature), a layer such as the native AlO X or in general metalsemiconductor interfaces are expected to have a high density of defect states [53,71,123]. An acceptable degree of operational stability can only be achieved with low defect density interfaces, e.g., prepared using self-assembled monolayers or Teflon-like dielectrics [20].…”

Section: Stability and Device Reliabilitymentioning

confidence: 99%