Quantum point contact with large subband energy spacings

Abstract

Quantum point contact (QPC) with an extra metallic gate in between the split gates of a conventional QPC was fabricated and studied. Clear conductance quantization was observed at 4.2 K when a proper positive voltage was set to the middle gate of the QPC. The maximum energy spacing between the ground and the first exited state of the QPC was around 7 meV which is at least a few times larger than that of conventional QPCs. Using same approach, a possibility of making a relatively clean and long 1D wire has been tested.

Electrostatically Induced Quantum Point Contacts in Bilayer Graphene

“…In a next step, a split gate geometry was added to the devices, which was then covered by another insulating layer and a gate on top of the channel. In GaAs, similar QPC gate geometries have been studied 10 . This gate combination allows us to define an electron channel with resistances exceeding 1000 × h/e 2 when depleted.…”

“…In GaAs, similar QPC gate geometries have been studied. 10 This gate combination allows us to define an electron channel with resistances exceeding 1000 × h/e 2 when depleted. The combination of top gates and back gate is essential to separately tune the gap and the position of the Fermi level in the regions underneath the split gates as well as the carrier density in the channel.…”

Multi-Valued Logic Gates based on Ballistic Transport in Quantum Point Contacts

“…Unlike the conventional QPCs, an extra middle gate (MG in the figure) was used in the gap of the QPC gates. By applying a positive voltage on the middle gate, the depth of the potential well in the QPC could be made deeper and sharper, thereby making the sub-band energy spacing a few times larger (~7 meV) than that of a conventional QPC 7 . This helps to observe clear conductance quantization at 4.2 K and fabricate a clean 1-dimensional conducting channel along the gate by minimizing the effects of unwanted potential fluctuations drawn by the ionized impurities in the modulation doping region.…”

Ultra‐Shallow All‐Epitaxial Aluminum Gate GaAs/AlxGa1−xAs Transistors with High Electron Mobility

“…There is a growing interest in defining increasingly smaller lithographic structures for nanoelectronic devices, both from research and industry sectors. From the point of view of the research sector, decreasing the size of nanoelectronic devices enables the study of quantum effects at higher temperatures, [ 1,2 ] whereas from an industry perspective, smaller devices lead to increased operation speed, packing density, and lower power usage. [ 3,4 ]…”