Quantum simulations of electrostatics in Si cylindrical junctionless nanowire nFETs and pFETs with a homogeneous channel including strain and arbitrary crystallographic orientations

Pham, Anh-Tuan; Sorée, Bart; Magnus, Wim; Jungemann, Christoph; Meinerzhagen, B.; Pourtois, Geoffrey

doi:10.1016/j.sse.2011.10.016

Cited by 3 publications

(2 citation statements)

References 22 publications

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“…Detailed measurements [14][15][16][17][18] , as well as atomistic scale simulations 19,20 were followed up by the same group. The success of the junctionless transistor has attracted great attention of both experimentalists and theorists [21][22][23][24][25] in the world.…”

Section: B Application On Junctionless Transistormentioning

confidence: 99%

New Multi-Scale Simulation Framework for Next-Generation Electronic Design Automation with Application to the Junctionless Transistor

Peng,

Chen,

Wong

et al. 2012

Preprint

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In this paper we present a new multi-scale simulation scheme for next-generation electronic design automation for nano-electronics. The scheme features a combination of the first-principles quantum mechanical calculation, semi-classical semiconductor device simulation, compact model generation and circuit simulation. To demonstrate the feasibility of the proposed scheme, we apply our newly developed quantum mechanics/electromagnetics method to simulate the junctionless transistors. The simulation results are consistent with the experimental measurements and provide new insights on the depletion effect of the hetero-doped gate on the drain current.Based on the calculated I-V curves, a compact model is then constructed for the junctionless transistors. The validity of the compact model is further verified by the transient circuit simulation of an inverter.

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Section: B Application On Junctionless Transistormentioning

confidence: 99%

New Multi-Scale Simulation Framework for Next-Generation Electronic Design Automation with Application to the Junctionless Transistor

Peng,

Chen,

Wong

et al. 2012

Preprint

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“…In some reported JLTs, highly doped and thin channel were implemented to provide enough carriers into the channel in the on state and reach to complete depletion in the off state (Colinge et al , 2011). However, in ultra-thin heavily doped silicon because of the conjunction of ionized impurity scattering, mobility of the carriers generally degrades significantly (Pham et al , 2012). The fabrication of p-type side gate junctionless transistor (SGJLT) device with simple structure, low doping concentration and no gate oxide layer using unconventional method of atomic force microscopy nanolithography is already reported in the study by Dehzangi et al (2012).…”

Section: Introductionmentioning

confidence: 99%

Study of the side gate junctionless transistor in accumulation region

Dehzangi

Larki

Ali

et al. 2016

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Purpose The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition. Design/methodology/approach The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 μm for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley–Read–Hall (SRH) carrier recombination/generation. Findings We have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components’ variation, carrier’s concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers’ movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime. Originality/value The proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results.

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