Quantum Transport in AlGaSb/InAs TFETs With Gate Field In-Line With Tunneling Direction

Jiang, Zhengping; Lu, Yeqing; Tan, Yaohua; He, Yu; Povolotskyi, Michael; Kubis, Tillmann; Seabaugh, Alan; Fay, Patrick; Klimeck, Gerhard

doi:10.1109/ted.2015.2443564

Cited by 11 publications

(2 citation statements)

References 6 publications

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“…The 3HJ TFETs are thus very promising in future fast low-power computing applications. The model developed in this work can be used to study the effects of carrier thermalization and serial resistance in a variety of highcurrent TFETs, especially those featuring a potential notch in the source [5], [30], [31].…”

Section: Discussionmentioning

confidence: 99%

A Multiscale Modeling of Triple-Heterojunction Tunneling FETs

Huang

Long

Povolotskyi

et al. 2017

IEEE Trans. Electron Devices

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A high performance triple-heterojunction (3HJ) design has been previously proposed for tunneling FETs (TFETs). Compared with single heterojunction (HJ) TFETs, the 3HJ TFETs have both shorter tunneling distance and two transmission resonances that significantly improve the ON-state current ($I_{\rm{ON}}$). Coherent quantum transport simulation predicts, that $I_{\rm{ON}}=460\rm{\mu A/\mu m}$ can be achieved at gate length $Lg=15\rm{nm}$, supply voltage $V_{\rm{DD}}=0.3\rm{V}$, and OFF-state current $I_{\rm{OFF}}=1\rm{nA/\mu m}$. However, strong electron-phonon and electron-electron scattering in the heavily doped leads implies, that the 3HJ devices operate far from the ideal coherent limit. In this study, such scattering effects are assessed by a newly developed multiscale transport model, which combines the ballistic non-equilibrium Green's function method for the channel and the drift-diffusion scattering method for the leads. Simulation results show that the thermalizing scattering in the leads both degrades the 3HJ TFET's subthreshold swing through scattering induced leakage and reduces the turn-on current through the access resistance. Assuming bulk scattering rates and carrier mobilities, the $I_{\rm{ON}}$ is dropped from $460\rm{\mu A/\mu m}$ down to $254\rm{\mu A/\mu m}$, which is still much larger than the single HJ TFET case

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Section: Discussionmentioning

confidence: 99%

A Multiscale Modeling of Triple-Heterojunction Tunneling FETs

Huang

Long

Povolotskyi

et al. 2017

IEEE Trans. Electron Devices

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“…More importantly, the performance comparisons are fair within the current framework, as identical mathematical and physics models are employed in all devices across the board. Nonetheless, the absolute accuracy of the reported performance parameters could be improved, if full-3D simulations with a more rigorous solution of underlying quantum mechanical transport problem can be attempted [14].…”

Section: Device Structures and Modelingmentioning

confidence: 99%

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

Canan

Kaya

Kodi

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to ×10) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance. INDEX TERMS 3T-XOR, 4T AND-OR-invert (AOI), 6T 4-to-1 multiplexer (MUX), ambipolar, CMOS logic gates, nanotechnology, Schottky-barrier MOSFET, tunneling.

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Modeling of Graphene‐Based Electronics: From Material Properties to Circuit Simulations

2019

Handbook of Graphene

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Quantum Transport in AlGaSb/InAs TFETs With Gate Field In-Line With Tunneling Direction

Cited by 11 publications

References 6 publications

A Multiscale Modeling of Triple-Heterojunction Tunneling FETs

A Multiscale Modeling of Triple-Heterojunction Tunneling FETs

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

Modeling of Graphene‐Based Electronics: From Material Properties to Circuit Simulations

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