Quasi-Complementary BiCMOS For Sub-3-V Digital Circuits

Yano, Kazuo; Hiraki, M.; Shukuri, S.; Sawahata, Yasushi; Hirao, M.; Ohki, N.; Nishida, Takashi; Seki, Kazuhiko; Shimohigashi, K.

doi:10.1109/vlsic.1991.760109

Cited by 20 publications

(2 citation statements)

References 13 publications

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“…(5] is briefly reviewed as follows. As shown in Fig.l(a) where Vgs is the gate-source voltage, Vdd is the supply voltage, and V h is the baseemitter voltage when the bipolar transistor is turned on.…”

Section: Introductionmentioning

confidence: 99%

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Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit

Tseng

Cheng²,

Wu³

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

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This paper describes a new feedbackcontrolled ehanced-pull-down BiCMOS (FC-EPD-BiCMOS) logic scheme for the low-supply-voltage operation. Through the use of the feedback-controlled enhanced-pull-down structure, the driving capability is improved and biploar transistor saturation during operation period is avoided. Based upon the proposed structure, both static and differential logic gates are developed. The new BiCMOS three-input NAND gate offers 35% reduction in the propagation delay time as compared to conventional BiCMOS circuits at 2.5 V supply voltage. The proposed three-input FC-EPD-BiCMOS CPL XORlXNOR gate has 33% improvement in delay time as compared to conventional BiCMOS 3input XORKNOR gates at 2.4 V supply voltage.

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Section: Introductionmentioning

confidence: 99%

“…The schematic inverter configuration of the QC-BiCMOS [5] is shown in Fig.l@). The base of the n-pn biploar transistor 4 2 is driven by the PMOS MP2.…”

Section: Introductionmentioning

confidence: 99%