R<sup>2</sup>-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies

Park, Jaeseok; Cheong, Minho; Kang, Sungho

doi:10.1109/tr.2017.2681103

Cited by 17 publications

(13 citation statements)

References 22 publications

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“…The ratio of the spare TSVs to the signal TSVs in a group is decided based on the acceptable yield and the quality of the manufacturing process. A more reliable manufacturing process requires less number of spare TSVs (for a given number of signal TSVs) to be specified in design [20]. Rerouting can be implemented using either the fuse technology or switching [20].…”

Section: Previous Workmentioning

confidence: 99%

“…The fact that many of the spare TSVs are not utilized highlights the inefficiency in existing approaches. Based on this observation, the authors in [20] proposed an online testing and soft error detection architecture for further enhancing the reliability of 3-D integrated circuits by utilizing the redundant TSVs that are left unused in the repair process. In this architecture, response compactors at the input and output of the TSVs are used for error detection.…”

Section: Previous Workmentioning

confidence: 99%

“…The proportion of redundant TSVs in a group depends on the reliability of the manufacturing process. Not all the redundant TSVs are utilized in the repair process and many of the TSVs are reduced to mere additional metal lines in the substrate, a fact known as the inefficiency in TSV redundancy utilization [20]. Keeping in view the challenges posed by TSV based 3-D integration technology, we propose a TSV virtualization based repair architecture utilizing multi-bit transmission through a single TSV channel.…”

Section: Introductionmentioning

confidence: 99%

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Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

et al. 2020

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Three-dimensional (3-D) integration offers a promising solution to the technology scaling barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of the underlying interconnect. Through Silicon Via (TSV) based 3-D ICs would suffer from low yield due to the faults in TSVs. In addition, TSVs introduce stress and noise in the substrate. Adding redundant TSVs for repairing the faulty ones has commonly been proposed to improve the yield of TSV-based 3-D ICs. The existing TSV repair approaches employ a number of spare TSVs in a group of signal TSVs. We propose a TSV virtualization based repair architecture which utilizes a single redundant TSV to repair multiple faulty TSVs. The proposed architecture relies on transmitting multiple bits through a single TSV using multi-level voltage quantization. It makes efficient use of the TSV redundancies in repairing the faulty TSVs. With less number of spare TSVs, the proposed architecture can reduce the area overhead by more than 70%. Reduction in the TSV count allows greater interconnect density and helps to mitigate the TSV-induced noise and stresses. Alternatively, for a similar number of spare TSVs, the proposed method can enhance the fault tolerance capability of the conventional approaches thus leading to an enhanced chip yield. The eye diagram simulations using an electrical model of the TSV show a reduction of less than 5% in noise margin when using a 16-level voltage quantization at a data rate of 5 Gbps which is typical for 3-D integration applications. INDEX TERMS 3-D integrated circuit, eye diagram simulations, multiple bits transmission, through silicon via (TSV), TSV Virtualization, TSV repair.

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Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

et al. 2020

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“…Postbond test is also required since new defects may appear during the bonding process, and some defects that appeared during the prebonding stage might not have been detected. As TSV yield may still not be satisfactory, redundancy TSVs and self-repairing mechanisms for each TSV could be included to ensure full functionality of 3-D ICs [8]- [12].…”

mentioning

confidence: 99%

“…As far as prebond testing is concerned, TSVs are too small for a test probe, and the number of test probe pads required is not affordable. Thus, although research is devoted to overcoming such disadvantages [8]- [14], the prebond test of TSVs is still challenging. As an alternative to probe testing, built-in self-test (BIST) structures have been proposed to detect the presence of a defective TSV.…”

mentioning

confidence: 99%

Postbond Test of Through-Silicon Vias With Resistive Open Defects

Rodríguez-Montañés

Arumí

Figueras

2019

IEEE Trans. VLSI Syst.

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Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are critical elements susceptible to undergoing defects at steps, such as fabrication and bonding or during their lifetime. Resistive open defects have become one of the most frequent failure mechanisms affecting TSVs. They include microvoids, underfilling, misalignment, pinholes in the oxide, or misalignment during bonding, among others. Although considerable research effort has been made to improve the coverage of TSV testing, little attention has been paid to weak (resistive) open defects causing small delays. In this work, a postbond oscillation test strategy to detect such small delay defects is proposed. Variations in the duty cycle of transmitted signals after unbalanced logic gates are shown to help in the detection of weak open defects in TSVs. HSPICE simulations, including process parameter variations, have been considered, and results show the effectiveness of the method in the detection of weak open defects above 1 k . Experimental work on a 65-nm IC also corroborates the detection capability of the proposal. Index Terms-Design for testability, duty cycle (DC), resistive open defect, three-dimensional integrated circuit (3-D IC), through-silicon via (TSV), TSV testing.

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A co-optimization method of thermal-stress coupling 3D integrated system with through silicon via

Wang,

Chen,

et al. 2023

Struct Multidisc Optim

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R²-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies

Cited by 17 publications

References 22 publications

Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

Postbond Test of Through-Silicon Vias With Resistive Open Defects

A co-optimization method of thermal-stress coupling 3D integrated system with through silicon via

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R2-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies

Cited by 17 publications

References 22 publications

Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

Postbond Test of Through-Silicon Vias With Resistive Open Defects

A co-optimization method of thermal-stress coupling 3D integrated system with through silicon via

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Product

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R²-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies