Rad-Hard 32 nm FinFET Based Inverters

Abstract

This paper reports a novel circuit level hardening technique that can decrease sensitivity to radiation induced single event upsets in 32nm FinFET based circuits. Five different types of 32 nm FinFET based inverters are analyzed. Proposed design outperforms over the unhardened circuit when exposed to radiation. This is majorly due to the innovative design technique used to neutralize effect of single event upset without affecting normal operation. Effect of back gate voltage and back gate oxide thickness variation is reported. Results indicate that the proposed design has good hardness to single event upset but has little area and power overheads than the unhardened FinFET based design.

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

“…However, the sensitive area is proportionally increased, especially in complex gates, due to the large increase of direct connection of the drain transistor to the gate output. Another solution, Rad-hard, another possible solution, attempts to change the source voltage of the transistor in order to obtain less sensitivity to a SET [32]. Neither addresses the problem of noise immunity.…”