Extreme Environment Electronics 2017
DOI: 10.1201/b13001-15
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Radiation Effects in Si CMOS Platforms

Abstract: IntroductionPredicting the rate of occurrence of single event effects (SEEs) By the early 1990s it was becoming clear that CRÈME and the other early models needed https://ntrs.nasa.gov/search.jsp?R=20120016823 2018-05-12T09:45:40+00:00Z

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Cited by 1 publication
(2 citation statements)
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References 78 publications
(132 reference statements)
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“…14 to 17 would indicate that the device is expected to become progressively more resistive at the gate input, which is exacerbated in large gate width devices. This is consistent with previous findings [17] that smaller devices are less susceptible to TID damage. On the contrary, the output impedance is expected to remain largely unaffected by TID, as is evident from Figs.…”
Section: 4predicted S-parameter Variationsupporting
confidence: 94%
See 1 more Smart Citation
“…14 to 17 would indicate that the device is expected to become progressively more resistive at the gate input, which is exacerbated in large gate width devices. This is consistent with previous findings [17] that smaller devices are less susceptible to TID damage. On the contrary, the output impedance is expected to remain largely unaffected by TID, as is evident from Figs.…”
Section: 4predicted S-parameter Variationsupporting
confidence: 94%
“…The trapped charges can shift the threshold voltage, increasing Rg and reducing gm. Trapped charges can further cause a reduction in the mobility of the device and an increase in the surface resistivity in the lightly doped drain [17], [18]. An increase in the surface resistivity of the drain leads to an increase in Rds and Rbb.…”
Section: 1extracted Parameter Datamentioning
confidence: 99%