Radiation-Hardened Design of Nonvolatile MRAM-Based FPGA

Abstract

Field-programmable gate arrays (FPGA) based on static random access memory (SRAM) are more common than other types, including flash and anti-fuse because of their infinite configurability and high performance. However, following the scaling down of CMOS technology, standby power of the CMOS circuits are becoming crucial. Logic circuits based on magnetic RAM (MRAM) can be attractive replacement for the SRAM-based logics thanks to their zero leakage and CMOS compatibilities. Furthermore, in FPGA design, using MRAM logic instead of SRAM logic results in some more advantages including non-volatility and high radiation reliability. In this paper, effects of radiation induced soft errors on MRAM-based FPGAs (MFPGA) is taken into account. Soft error tolerance of the previous MFPGAs are discussed and a new MFPGA structure is proposed. It is shown that, the proposed non-volatile, low power and high speed MFPGA is highly robust against radiation induced soft errors. It also is shown that, the proposed MFPGA offering a high radiation robustness does not incur a considerable design overhead comparing with the other similar MFPGAs.

NVRH-LUT: A nonvolatile radiation-hardened hybrid MTJ/CMOS-basedlook-up table for ultralow power and highly reliable FPGA designs

“…[18] Ref. [19] Proposed NVRH-LUT Normal zed BER LUT4 LUT5 LUT6 Figure 8. Comparison of the PV effects in different STT-LUT circuits.…”

Design of a Radiation Hardened Register File for Highly Reliable Microprocessors

“…In this approach, radiation tolerance is obtained by a new design in circuit level. Radiation hardening by design can offer a high degree of reliability at the expense of a low design overhead [21][22]. However, they need specific fabrication process and high nonrecurring engineering (NRE) cost.…”

“…However, they need specific fabrication process and high nonrecurring engineering (NRE) cost. Various circuits designed in [3,5,21,23] offer SEU tolerance by design.…”

“…9 and Fig.10, a comparison is made for normalized area overhead and reliability achievement of the TMR, our proposed technique, half protected using our technique and half protected using Hamming(7,4), Hamming (21,16) and DMR. As can be seen from the results presented in these figures, depending on the application a desirable trade-off for reliability and area can be found.…”

Soft/write-error-resilient CMOS/magnetic tunnel junction nonvolatile flip-flop based on majority-decision shared writing

“…Recently, only the issues of SEUs have been addressed for CMOS=MTJ hybrid integrated circuits. 18,19) In this paper, both write-and soft-error issues including SETs and SEUs are addressed by our proposed majoritydecision shared-writing scheme for CMOS=MTJ-based NVFFs. Figure 1 shows a three-terminal MTJ device that can be mainly implemented on the basis of domain-wall motion (DWM) devices and spin-orbit-torque devices.…”