Radix $r^{k} $ FFTs: Matricial Representation and SDC/SDF Pipeline Implementation

Abstract

This paper proposes to use the discrete Fourier transform (DFT) matrix factorization based on the Kronecker product to express the family of radix single-path delay commutator/ single-path delay feedback (SDC/SDF) pipeline fast Fourier transform (FFT) architectures. The matricial expressions of the radix , 2 , 3 , and 4 decimation-in-frequency (DIF) SDC/SDF pipeline architectures are derived. These expressions can be written using a small set of operators, resulting in a compact representation of the algorithms. The derived expressions are general in terms of and the number of points of the FFT . Expressions are given where it is not necessary that is a power of . The proposed set of operators can be mapped to equivalent hardware circuits. Thus, the designer can easily go from the matricial representations to their implementations and vice versa. As an example, the mapping of the operators is shown for radix 2 2 2 , 2 3 , and 2 4 , and the details of the corresponding SDC/SDF pipeline FFT architectures are presented. Furthermore, a general expression is given for the SDC/SDF radix pipeline architectures when4. This general expression helps the designer to efficiently handle a wider design exploration space and select the optimum single-path architecture for a given value of .

Fast Fourier Transform Processors: Implementing FFT and IFFT Cores for OFDM Communication Systems

“…Within each stage, there is a sequence of hardware processing elements which can perform the computations defined by the operators presented in Section 2.2 as illustrated in the second and third rows of Figure 1. The hardware required to implement the computations demanded by each operator is discussed in (Cortés et al, 2009). It is important to note that the shuffling operators surrounding the butterfly operators can be merged in the single device with feedback typical of the SDF architecture.…”

“…However, that notation is not generalized for pipeline architectures. Recently, (Cortés et al, 2009) generalized the above approach presenting a unified approach for radix r k pipeline SDC/SDF FFT architectures. Radix r k pipeline FFT architectures are very efficient architectures that are well suited for OFDM systems.…”

“…The case study analyzes the FFT/IFFT processor in a WLAN IEEE 802.11a transceiver. The high level analysis proposed in (Cortés et al, 2009) is extended to implementation level to select the most efficient FFT/IFFT core in terms of area and power consumption.…”

4k-point FFT algorithms based on optimized twiddle factor multiplication for FPGAs

“…x (16) x (17) x (18) x (19) x (20) x (21) x (22) x (23) x (24) x (25) x (26) x (27) x (28) x (29) x (30) x (31) x (0) x (2) x (3) x (4) x (5) x (6) x (7) x (8) x (9) x (10) x (11) x (12) x (13) x (14) x (15) x (1) W0,25 W0,27…”

Tunable Mixed Decimation Multipath Delay Feedback for Radix 2k FFT

“…The single path delay commutators (SDC) [2] are the most popular technique in the serial input and serial output scenarios. Single path delay feedback (SDF) architecture is proposed to reduce the memory banks in the pipelines [3]. The SDF concept extended to radix 2 to radix 2 k [4][5][6].…”