Diffusers are found to play a significant role in the performance of centrifugal compressors. Extensive studies have been in progress in various research laboratories for improvement of performance with various types of diffusers. One such effort for study of performance of a centrifugal compressor stage with Low Solidity Diffuser (LSD) vanes is presented in this paper. The study was conducted at a tip mach number of 0.35. An exclusive test rig was set up for carrying out these flow studies. The LSD vane is formed using standard NACA profile with marginal modification at the trailing edge region. The study encompasses the variation of setting angle of the LSD vane and the vane solidity. The effect of solidity and the setting angle on overall stage performance is evaluated in terms of flow coefficient, head coefficient and efficiency normalised with respect to these parameters for the case of vaneless diffuser at design flow. Improvement in performance as well as static pressure recovery was observed with LSD as compared to vaneless diffuser configuration. It is concluded from these studies that there is an optimum solidity and stagger angle for the given stage with LSD vanes for the chosen configuration.

A new method to obtain a high frequency clock (1 GHz)

The results of experimental studies on a centrifugal compressor stage using uncambered constant thickness low solidity diffuser vanes (LSD) are reported in this paper. In the present work, efforts are concentrated for study of stage performance with LSD vanes for a typical compressor stage at a tip mach number of 0.35. The effect of solidity and setting angle on overall stage performance is evaluated in terms of flow coefficient, head coefficient and efficiency. The results were normalised with the data available at design flow using vaneless diffuser. Improvement in performance as well as static pressure recovery was observed with LSD vanes of the chosen configuration as compared to vaneless diffuser configuration. Variation of blade loading is studied from the measurements of static pressure on pressure and suction surfaces of LSD vane.

The Decimation Multipath Delay Feedback (M 2 DF) is a technique for the radix 2 k FFT, which eliminates the stand by time of arithmetic modules in computing units. In this paper tunable M 2 DF architecture is proposed. In this, tunable arithmetic units are utilized in place of conventional arithmetic units to overcome the under utilization of arithmetic units in conventional M 2 DF architecture. The results show that, the tunable M 2 DF technique utilizes the lesser number of LUTs and slice registers than the conventional M 2 DF technique. In addition, the proposed technique having advantage of high throughput with reduced delay and area compared with conventional M 2 DF.Copy Right, IJAR, 2018,. All rights reserved. …………………………………………………………………………………………………….... Introduction:-Fast Fourier Transform (FFT) is mostly used algorithm for Discrete Fourier Transform computation in the field of signal processing. The area efficient and high performance FFT implementation throws a challenge on the designers. Hardware designers are putting effort to design effectual architectures for the computation of the FFT to meet required specifications and real-time fulfillment of present applications. Various techniques have proposed over the years to tradeoff the area and performance of the FFT. Pipelined architectures [1] are extensively used because they will achieve more throughputs and small latencies relevant for today's applications to achieve small area and to dissipate less power. The single path delay commutators (SDC) [2] are the most popular technique in the serial input and serial output scenarios. Single path delay feedback (SDF) architecture is proposed to reduce the memory banks in the pipelines [3]. The SDF concept extended to radix 2 to radix 2 k [4][5][6]. The high throughput requirements of communication services encouraged to multipath delay commutators [7] and multipath delay feedback (MDF) [8].The MDF structures are formed using multiple interconnected SDFs. The MDF scheme is utilized in various applications due to its efficient memory usage, but suffers from arithmetic resource utilization and it is rectified in M 2 DF architecture [9], which utilizes the folding transformation technique for the significant reduction of arithmetic resources.In this work, tunable M 2 DF architecture is proposed to further reduce the arithmetic operations in terms of number of LUTs and registers.Construction of M 2 DF Architecture:-Design of parallel radix-2 k FFT processor based on folding transformations to derive the folding matrices of DIF and DIT of SDF structures. The pipelined structure is rescheduled by incorporating DIF blocks into DIT blocks to form

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