RAM cell recovery mechanisms following high-energy ion strikes

Basic mechanisms and modeling of single-event upset in digital microelectronics

“…Even the particle with LET well below the upset threshold causes a significant voltage transient on SET at the struck drain. Whether an observable SEU occurs depends on which happens faster: the feedback of the voltage transient through the opposite inverter, or recovery of the struck node voltage as the single-event current dies out [58], [76], [77]. Note that drift (including funneling effects) is responsible for the rapid initial flip of the cell, while long-term charge collection by diffusion prolongs the recovery process; both mechanisms are critical to the upset process.…”

“…From a technology standpoint, the recovery time depends on the restoring transistor current drive and minority carrier lifetimes in the substrate [76], [77]. The cell feedback time is simply the time required for the disturbed node voltage to feed back through the cross-coupled inverters and latch the struck device in its disturbed state.…”

“…The inherently 3-D nature of an ion passing through a microelectronic device is difficult to address with the 2-D simulation programs that are routinely used in the semiconductor industry for device analysis. The development of full 3-D tools has been fairly recent, however, and much insight has been gained in the past through the use of 2-D programs [48], [50], [61], [74], [76], [77], [126]- [133].…”

Three-dimensional simulation of charge collection and multiple-bit upset in Si devices

“…In a nonhardened cell with low restoring transistor drive, a short current pulse may be more detrimental. The interplay between the struck device and the external circuitry is thus of primary importance to determining cell upset characteristics [33]. This underscores the need to include external circuitry and loading effects in simulations if SEU sensitivity, and not just charge collection, is to be addressed.…”

“…The actual response will depend on the details of the SRAM cell, particularly gate and drain capacitances, the feedback resistance in resistively-hardened cells, and the current drive of the restoring transistor. SEU ultimately results when the recovery time of the cell (time required for the struck node to recover to near its pre-strike value) exceeds the feedback time (time required for the disturbed node potential to feed back into the struck node and become latched as incorrect data) [33]. In a cell hardened by increasing the feedback time (e.g.. resistive hardening).…”