Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal–Oxide–Semiconductor Field-Effect Transistors

Putra, A.T.; Nishida, Akio; Kamohara, S.; Hiramoto, Toshiro

doi:10.1143/apex.2.024501

Cited by 36 publications

(26 citation statements)

References 7 publications

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“…25) Similar effects have been observed in the transistor variability due to gate line width roughness (LWR), where V TH variability saturate as the gate width becomes narrower than the correlation width. 25) The differences between W dependence and L dependence in Figs. 8 and 10 suggest that the averaging mechanisms in the W and L directions are not the same.…”

Section: Simulation Resultsmentioning

confidence: 59%

Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

Kumar¹,

Mizutani²,

Hiramoto³

2012

Jpn. J. Appl. Phys.

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This paper presents the statistical analysis of a newly found drain current variability component called ''current-onset voltage'' (COV) variability as well as drain induced barrier lowering (DIBL) variability in bulk and fully-depleted (FD) silicon-on-insulator (SOI) devices. Intensive variability measurement data show that gate length and gate width dependent COV variability and DIBL variability in bulk metal-oxide-semiconductor field effect transistors (MOSFETs) deviate from the straight line in the Pelgrom plot. On the other hand, COV variability and DIBL variability in FD SOI MOSFETs fall on the straight line. Their mechanisms are discussed based on three-dimensional (3D) device simulation considering random dopant fluctuation (RDF). It is found that the saturation of the COV and DIBL variability in smaller devices is caused by weaker averaging effect of channel potentials. #

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Section: Simulation Resultsmentioning

confidence: 59%

Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

Kumar¹,

Mizutani²,

Hiramoto³

2012

Jpn. J. Appl. Phys.

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“…22 This is a significant amount considering that the present-day ULSIs require V th variability of less than 10 mV. 7,[16][17][18][19]26,28 Finally, we summarize simulated results of DV th and I off variations for two f Eion (x) cases in Figs. 7 and 8, respectively.…”

Section: A Threshold Voltage Versus E Ionmentioning

confidence: 99%

“…17,19,21,22 Aggressively scaled MOSFETs beyond 32 nm node require the V th variation to be suppressed to less than 10 mV. 7 Due to this requirement, there have been extensive studies on suppression of r Lg , 7 line-edge roughness (LER), 19,[25][26][27] and line-width roughness (LWR), 7,19,28 during gate-etch processes. These studies focused on controlling the reactions on material surfaces governed by plasma chemistry.…”

Section: Introductionmentioning

confidence: 99%

Modeling of plasma-induced damage and its impacts on parameter variations in advanced electronic devices

Eriguchi

Takao

Ono

2011

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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A comprehensive model predicting the effects of plasma-induced damage (PID) on parameter variations in advanced metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. The model focuses on the silicon recess structure (Si loss) in the source/drain extension region formed by high-energy ion bombardment during plasma etching. The model includes the following mechanisms: (1) damaged layer formation by ion impact and penetration, (2) Si recess structure formation by a subsequent wet etch, (3) MOSFET performance degradation, and (4) MOSFET parameter variation. Based on a range theory for plasma-etch damage, the thickness of the damaged layer exhibits a power-law dependence on the energy of the ion incident on the surface of Si substrate. Assuming that the damaged layer was formed during a gate or an offset spacer etch process, the depth of Si recess (d R ) is a function of the depth profile of the created defect site (n dam ), the wet-etch stripping time (t w ), and the energy of the incident ion. It was found that d R also showed a power-law dependence on the average ion energy E ion estimated from applied self-dc-bias voltage for various t w . As for MOSFET performance degradation, the threshold voltage (V th ) shifted and the shift (DV th ) increased with an increase in E ion and a decrease in gate length. This induces an increase in subthreshold leakage current (I off ) for MOSFET. Technology computer-aided-design simulations were performed to confirm these results. By integrating the presented PID models, parameter variations could be predicted: Using a Monte Carlo method, it was demonstrated that PID increases parameter variations such as V th and I off . It also was found that the variation in E ion induces V th and I off variations, comparable to that induced by other process parameter fluctuations such as dopant fluctuation and gate length. In summary, considering the effects of PID on parameter variations is vital for designing future ultralarge-scale-integrated circuits with billions of built-in MOSFETs.

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“…Because of this orthogonal-size dependence, the intradevice averages get more widely distributed with the scaling down, and the threshold voltages are further scattered as a result. 17,25 On-state currents of MOSFETs are also affected by this process 15,16,18,26 both indirectly through the above threshold-voltage change and directly as seen from the operation principle of MOSFETs. 27 Additionally, interconnect layers of LSIs have recently been shown to be prone to LER-driven degradation of timedependent-dielectric-breakdown reliability between neighboring wirings.…”

Section: Introductionmentioning

confidence: 99%

Spectral analysis of line edge and line-width roughness with long-range correlation

Hiraiwa

Nishida

2010

Journal of Applied Physics

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Large-scale integrations (LSIs) are facing an ever-growing problem of device variability. One of the origins that cause the variability is line-width roughness (LWR) caused by line edge roughness (LER). Accurate characterization of the LWR plays an essential role in controlling the LWR. To do this, we report a methodology, named the “assembly method,” that enables to analyze LWR statistics beyond the conventional correlation length limit, basing on the previous “patchwork” method and recent discrete power spectral density (PSD) method. The methodology virtually assembles a long line by gathering line segments that are randomly scattered on a single line or equally processed different lines. The virtual lines are repeatedly assembled by randomly changing the combination of the segments and the order of the gathered segments while permitting overlaps of the segments between the assembled lines. Squared Fourier transforms of their widths are averaged over the assembled lines to obtain the PSD. By these steps, the statistical noise, which is inherent to experimental PSDs, is markedly reduced. Furthermore, to extract LWR statistics by comparing experimental and theoretical PSDs, we derived an analytic formula of the assembled-line PSD. In the derivation, the randomness of the segment collections played a key role. The PSDs calculated using the formula almost completely fitted experimental PSDs that were obtained by the assembly method. The parameters used in the best-fitted calculation revealed that the photoresist LWR of this study contained a component that had a correlation length of 2780 nm in addition to the previously reported LWR of 35 nm. The LWR variance of the component accounted for approximately 10% of the total variance. The formula also enabled us to evaluate the accuracy of experimentally obtained averages of widths. We find two distinct features in the PSDs by the assembly method. One is the oscillatory structure that shows up in the case when the correlation length is larger than half the length of the segments. A trace of this structure was actually observed in the experimental PSDs of this study. The other is the spikes that are periodically observed as a function of wave number. The spikes originate from a nonstochastic width variation that exists in all the segments in common. Their intensity is proportional to the number of gathered segments in the assembled lines. Because the spikes are excluded from the analysis, the LWR parameters determined by the assembly method are not affected by the nonstochastic variation, unlike the conventional methods. By all these results, we confirm that the assembly method of this study extends the upper limit of analyzable correlation lengths by a factor of approximately 20 and enhances the accuracy as well. This feature also has a practical significance that the widely observed LWR with a correlation length of approximately 35 nm can be analyzed by the assembly method using a conventional critical-dimension scanning-electron-microscope, without resorting to a specially designed one. Accordingly, the method will be a key tool for investigating LER and LWR in developing and manufacturing LSIs. It will also help analyze other stochastic processes in many research and development settings.

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Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal–Oxide–Semiconductor Field-Effect Transistors

Cited by 36 publications

References 7 publications

Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

Modeling of plasma-induced damage and its impacts on parameter variations in advanced electronic devices

Spectral analysis of line edge and line-width roughness with long-range correlation

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