Rapid circuit-specific inlining tuning for FPGA high-level synthesis

Noronha, Daniel Holanda; Pinilla, Jose P.; Wilton, Steven J. E.

doi:10.1109/reconfig.2017.8279807

Cited by 3 publications

(1 citation statement)

References 3 publications

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“…Tuning parameters on a circuit-by-circuit basis can be slow since it is difficult to obtain detailed estimates of candidate optimisation choices. [19] presents a novel hashing mechanism that accelerates the inlining optimisation using a two-level hash structure and quantifies its impact on run-time. [20] proposes to use machine learning to auto-tune the performance and power consumption of FPGA designs.…”

Section: E Comparison With Previous Workmentioning

confidence: 99%

Towards In-Circuit Tuning of Deep Learning Designs

Que

Noronha

Zhao

et al. 2019

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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This paper presents InTune, a novel approach for incircuit tuning of deep learning designs targeting implementations in field-programmable gate array technology. This approach combines two promising techniques: domain-specific adaptation and in-circuit tuning. Domain-specific adaptation exploits domainspecific information in adapting pre-trained models to specific application domains, replacing standard convolution layers with efficient convolution blocks; the effects of such adaptation are then assessed by in-circuit tuning instruments to provide information to application builders for tuning the design. This approach is illustrated by its deployment in tuning deep neural networks, and its potential for a new generation of domain-specific tools with tight integration of synthesis and in-circuit tuning is explored.

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Section: E Comparison With Previous Workmentioning

confidence: 99%

Towards In-Circuit Tuning of Deep Learning Designs

Que

Noronha

Zhao

et al. 2019

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design

Silva

Boyer

Langlois

2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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High-Level Synthesis (HLS) brings FPGAs to audiences previously unfamiliar to hardware design. However, achieving the highest Quality-of-Results (QoR) with HLS is still unattainable for most programmers. This requires detailed knowledge of FPGA architecture and hardware design in order to produce FPGA-friendly codes. Moreover, these codes are normally in conflict with best coding practices, which favor code reuse, modularity, and conciseness.To overcome these limitations, we propose Module-per-Object (MpO), a human-driven HLS design methodology intended for both hardware designers and software developers with limited FPGA expertise. MpO exploits modern C++ to raise the abstraction level while improving QoR, code readability and modularity. To guide HLS designers, we present the five characteristics of MpO classes. Each characteristic exploits the power of HLS-supported modern C++ features to build C++based hardware modules. These characteristics lead to highquality software descriptions and efficient hardware generation. We also present a use case of MpO, where we use C++ as the intermediate language for FPGA-targeted code generation from P4, a packet processing domain specific language. The MpO methodology is evaluated using three design experiments: a packet parser, a flow-based traffic manager, and a digital upconverter. Based on experiments, we show that MpO can be comparable to hand-written VHDL code while keeping a high abstraction level, human-readable coding style and modularity. Compared to traditional C-based HLS design, MpO leads to more efficient circuit generation, both in terms of performance and resource utilization. Also, the MpO approach notably improves software quality, augmenting parameterization while eliminating the incidence of code duplication.

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Formal verification of high-level synthesis

Herklotz

Pollard

Ramanathan

et al. 2021

Proc. ACM Program. Lang.

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High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language such as Verilog, while maintaining the convenience and the rich ecosystem of software development. However, current HLS tools cannot always guarantee that the hardware designs they produce are equivalent to the software they were given, thus undermining any reasoning conducted at the software level. Furthermore, there is mounting evidence that existing HLS tools are quite unreliable, sometimes generating wrong hardware or crashing when given valid inputs. To address this problem, we present the first HLS tool that is mechanically verified to preserve the behaviour of its input software. Our tool, called Vericert, extends the CompCert verified C compiler with a new hardware-oriented intermediate language and a Verilog back end, and has been proven correct in Coq. Vericert supports most C constructs, including all integer operations, function calls, local arrays, structs, unions, and general control-flow statements. An evaluation on the PolyBench/C benchmark suite indicates that Vericert generates hardware that is around an order of magnitude slower (only around 2× slower in the absence of division) and about the same size as hardware generated by an existing, optimising (but unverified) HLS tool.

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Rapid circuit-specific inlining tuning for FPGA high-level synthesis

Cited by 3 publications

References 3 publications

Towards In-Circuit Tuning of Deep Learning Designs

Towards In-Circuit Tuning of Deep Learning Designs

Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design

Formal verification of high-level synthesis

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