Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems

Javaid, Haris; Ignjatovic, Aleksander; Parameswaran, Sri

doi:10.1109/tcad.2010.2061353

Cited by 25 publications

(17 citation statements)

References 14 publications

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“…Pipelined MPSoCs have emerged as a viable platform for high throughput implementation of multimedia applications [6,9,10,11,12,13,7]. The works in [9,10,11] focus on balancing the pipelined MPSoC at design-time, while [6,12,13] have introduced adaptability in the pipelined MPSoCs to cope with run-time varying workloads of multimedia applications.…”

Section: Related Workmentioning

confidence: 99%

“…The works in [9,10,11] focus on balancing the pipelined MPSoC at design-time, while [6,12,13] have introduced adaptability in the pipelined MPSoCs to cope with run-time varying workloads of multimedia applications. Guo et al [13] proposed a dynamic voltage scaling approach to reduce the voltage to processors with low workload, while [6,12] showed the application of Dynamic Voltage and Frequency Scaling (DVFS) to pipelined MPSoCs.…”

Section: Related Workmentioning

confidence: 99%

“…The shrinkage of the dynamic range of voltage-frequency operational points due to downward scaling of supply voltage has also limited DVFS use, and has given rise to the use of dynamic power management with multiple power states. Our work uses the architecture proposed in [7] where an adaptive pipelined MPSoC with either power-gating or clock-gating is illustrated to provide energy savings over design-time balanced pipelined MPSoCs [9,10]. Our work uses multiple power states for APs in conjunction with application-aware dynamic power management scheme instead of power-and clock-gating the idle APs.…”

Section: Related Workmentioning

confidence: 99%

“…The following terms are used in addition to the ones described in Section 5: for which k-th AP will remain idle. For example, idleIterations[0] [10] = 3 means that AP0 will remain idle for the next 3 iterations starting at iteration 10, that is, until iteration 12. This table is populated using the workload prediction from the application.…”

Section: Application Prediction Based Heuristicsmentioning

confidence: 99%

“…The workload of each category in terms of the number of APs was computed using offline analysis and was saved in a lookup table for use at run-time. In our experiments, the ranges ( 1, 2 and 3) for predicted workload of low, medium and high motion MBs were [0, 4], [5,10] and [11,16] (number of APs) respectively. These ranges were also used by Algorithm 2 to compute the idleIterations table for the application prediction based heuristics.…”

Section: Implementation Detailsmentioning

confidence: 99%

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System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia

Javaid¹,

Shafique²,

Parameswaran³

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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System-level dynamic power management (DPM) schemes in Multiprocessor System on Chips (MPSoCs) exploit the idleness of processors to reduce the energy consumption by putting idle processors to low-power states. In the presence of multiple low-power states, the challenge is to predict the duration of the idle period with high accuracy so that the most beneficial power state can be selected for the idle processor.In this work, we propose a novel dynamic power management scheme for adaptive pipelined MPSoCs, suitable for multimedia applications. We leverage application knowledge in the form of future workload prediction to forecast the duration of idle periods. The predicted duration is then used to select an appropriate power state for the idle processor. We proposed five heuristics as part of the DPM and compared their effectiveness using an MPSoC implementation of the H.264 video encoder supporting HD720p at 30 fps. The results show that one of the application prediction based heuristic (MAMAPBH) predicted the most beneficial power states for idle processors with less than 3% error when compared to an optimal solution. In terms of energy savings, MAMAPBH was always within 1% of the energy savings of the optimal solution. When compared with a naive approach (where only one of the possible power states is used for all the idle processors), MAMAPBH achieved up to 40% more energy savings with only 0.5% degradation in throughput. These results signify the importance of leveraging application knowledge at system-level for dynamic power management schemes.

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