System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia

Abstract

System-level dynamic power management (DPM) schemes in Multiprocessor System on Chips (MPSoCs) exploit the idleness of processors to reduce the energy consumption by putting idle processors to low-power states. In the presence of multiple low-power states, the challenge is to predict the duration of the idle period with high accuracy so that the most beneficial power state can be selected for the idle processor.In this work, we propose a novel dynamic power management scheme for adaptive pipelined MPSoCs, suitable for multimedia applications. We leverage application knowledge in the form of future workload prediction to forecast the duration of idle periods. The predicted duration is then used to select an appropriate power state for the idle processor. We proposed five heuristics as part of the DPM and compared their effectiveness using an MPSoC implementation of the H.264 video encoder supporting HD720p at 30 fps. The results show that one of the application prediction based heuristic (MAMAPBH) predicted the most beneficial power states for idle processors with less than 3% error when compared to an optimal solution. In terms of energy savings, MAMAPBH was always within 1% of the energy savings of the optimal solution. When compared with a naive approach (where only one of the possible power states is used for all the idle processors), MAMAPBH achieved up to 40% more energy savings with only 0.5% degradation in throughput. These results signify the importance of leveraging application knowledge at system-level for dynamic power management schemes.

Applying Pay-Burst-Only-Once Principle for Periodic Power Management in Hard Real-Time Pipelined Multiprocessor Systems

“…Javaid et al [2011b] proposed an adaptive pipelined MPSoC architecture and a runtime balancing approach based on workload prediction to achieve energy efficiency. The authors in Javaid et al [2011a] proposed a dynamic power management scheme for adaptive pipelined MPSoCs. In this work, the duration of idle periods is determined based on future workload prediction and used to select an appropriate power state for the idle processor.…”

Adaptive and Hierarchical Runtime Manager for Energy-Aware Thermal Management of Embedded Systems

“…Based on this a thermal aware scheduling approach is proposed to reduce the temperature of the system at run-time. Apart from these works, there are other studies to reduce the power consumption of a multicore system by scaling the hardware frequency dynamically [Dhiman and Rosing 2009;Javaid et al 2011;Ye and Xu 2014;Khan and Rinner 2014]. However, as shown in [Faruque et al 2010], these approaches cannot guarantee to minimize a system's thermal overhead effectively for all applications.…”

“…As such, static compile-time policies [Rai et al 2011;Schor et al 2013;Das et al 2015a] (with limited knowledge of application-specific variations) are often outperformed, even by naive run-time managers, both in terms of thermal overhead and energy consumption -the two key design aspects of modern systems. This has motivated researchers in recent years to investigate run-time approaches, thriving the development of intelligent run-time systems for energy and thermal management [Cochran et al 2011b;Javaid et al 2011;Juan et al 2013;Ye and Xu 2014;Srinivasan et al 2004;Sharifi et al 2013;Shi et al 2013;Faruque et al 2010;Ge and Qiu 2011;Coskun et al 2009a;Mercati et al 2013;Das et al 2014;Coskun et al 2009b;Ebi et al 2009;Ebi et al 2011;Shen et al 2012].…”

Adaptive dynamic power management for hard real-time pipelined Multiprocessor Systems

“…Javaid et al [12] proposed a adaptive pipelined MPSoC architecture and a run-time balancing approach based on workload prediction to achieve energy efficiency. Authors in [11] proposed a dynamic power management scheme for the adaptive pipelined MPSoCs. In this work, the duration of idle periods is determined based on the future workload prediction and is used to select an appropriate power state for the idle processor.…”

“…Among multi-core architectures, pipelined multiprocessor architectures are believed to be one of promising computing paradigms for embedded system design, which can, in principle, provide high throughput and low energy consumption [2], [11], [12]. In pipelined multiprocessor architectures, processors are connected in a pipelined fashion via shared memory (e.g., FIFOs).…”