Rapid FPGA design prototyping through preservation of system logic: A case study

Haroldsen, Travis; Nelson, Brent; White, Brad

doi:10.1109/fpl.2013.6645539

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…The HD flow allows the partitioning of a design into multiple modules, which can be processed independently from each other. It was developed to provide a significant synthesis and implementation run time improvement by preventing unchanged logic from being re-implemented [10]. The HD flow is based on a script provided by Xilinx that we have adapted for meeting selftimed circuits timing constraints.…”

Section: Setup Holdmentioning

confidence: 99%

Self-timed circuits FPGA implementation flow

Fiorentino

Al-Terkawi

Savaria

et al. 2015

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)

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The conventional synchronous design approach is not suitable for implementing self-timed circuits on FPGAs. When design tools try to meet synchronous circuits timing constraints, they can violate self-timed setup timing constraints. This paper proposes a new methodology for implementing self-timed circuits in modern FPGAs using the Xilinx Hierarchical Design flow and a convenient architecture of a configurable delay element. Reported simulation results, in accordance with static timing analysis, show that the self-timed timing constraints are satisfied using our design methodology.

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Section: Setup Holdmentioning

confidence: 99%

Self-timed circuits FPGA implementation flow

Fiorentino

Al-Terkawi

Savaria

et al. 2015

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)

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“…It avoids optimization of those connections that is possible in usual compilation flow. As a result, QoR of modular design methodology is typically degraded [12].…”

Section: Introductionmentioning

confidence: 99%

Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network

Herath

Prakash

Srikanthan

2018

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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Modern FPGAs consist of millions of logic resources allowing hardware designers to map increasingly large designs. However, the design productivity of mapping large designs is greatly affected by the long runtime of FPGA CAD flow. To mitigate it, modular design methodology has been introduced in the past that allows designers to partition large designs into smaller modules and compile & test the modules individually before assembling them together to complete the compilation process. Automated decision making on placing these modules on FPGA, however, is a slow and tedious process that requires large database of precompiled modules, which are compiled on a large number of placement positions. To accelerate this placement process during modular designing, in this paper we propose an ANN based performance estimation technique that can rapidly suggest the best shape and location for a given module. Experimental results on legacy as well as state-of-the-art FPGA devices show that the proposed technique can accurately estimate the F max of modules with an average error of less than 4%.

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