In recent years, frameworks such as RapidSmith and Torc have been developed for the creation of custom CAD tools able to target actual Xilinx FPGA devices. These have been based on the Xilinx Design Language (XDL), which provides textual representations of both mapped user designs as well as detailed physical FPGA device descriptions. Vivado, Xilinx's new design suite, discontinues XDL and instead provides direct access to its data structures through a Tcl interface and through EDIF and constraint files. This paper formally introduces Tincr, a library of high-level Tcl routines that support the creation of custom circuit manipulation tools. A case study on the use of Tincr for the creation of a simple placement tool is given. Additionally, this paper describes Tincr's facilities for importing and exporting XDL-and XDLRC-like information to and from Vivado to allow the continued use of existing external CAD tool frameworks such as RapidSmith and Torc with Vivado.

FPGA designs often contain significant amounts of logic such as a board support package that remains unaltered throughout the design process. However, during normal operation, standard FPGA implementation tools re-implement the entire system, including the unchanged logic, adding to the turn around time of design iterations. Recently, FPGA implementation flows have appeared that allow preserving parts of a previously implemented design. In this study, we evaluate the potential speedups in implementation time achievable through preserving the unchanging portion of a design's implementation. We perform these evaluations using Xilinx Partitions, Xilinx SmartGuide, and the HMFlow rapid implementation tool.