Rapid search of Pareto fronts using D-logic exploration during multi-objective tradeoff of computation intensive applications

Sengupta, Anirban; Mishra, Vipul Kumar; Sarkar, Pallabi

doi:10.1109/asqed.2013.6643573

Cited by 3 publications

(3 citation statements)

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“…References [52][53][54] proposed an algorithm to explore the design space using binary search employing an ACG. Alternatively, the problem of DSE was addressed in [55,56] by a D-logic based exploration.…”

Section: Problem-specific Heuristic Approachesmentioning

confidence: 99%

Development of Multiobjective High-Level Synthesis for FPGAs

Bulnes

Maldonado

Trujillo

2020

Scientific Programming

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Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

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Section: Problem-specific Heuristic Approachesmentioning

confidence: 99%

Development of Multiobjective High-Level Synthesis for FPGAs

Bulnes

Maldonado

Trujillo

2020

Scientific Programming

View full text Add to dashboard Cite

show abstract

“…The functions to calculate P T and T E are adopted from Sengupta et al (2013). Figure 6.6 shows the process adopted to extract the hardware information for cost calculation.…”

Section: Model For Evaluation Of Particles (Design Points) During Mo-psementioning

confidence: 99%

“…where P T ¼ 6.55 W, T E ¼ 500.02 us, P Max ¼ 31.15 W, and T Max ¼ 500.02 us are evaluated from the models proposed in Sengupta et al (2013) and library assumed in . φ 1 ¼ φ 1 ¼ 0.5 is chosen for providing equal weightage to power and execution time factor while calculating fitness of particle.…”

Section: Cost Calculation Of Particlesmentioning

confidence: 99%