Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions

Abstract

This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. The key contributions of this paper are as follows: (1) a 4-way VLIW processor implemented in an FPGA, (2) large speedups through hardware functions, (3) a hardware/software interface with zero overhead, (4) a design methodology for implementing signal processing applications on this architecture, (5) tractable design automation techniques for extracting and synthesizing hardware functions. Several design tradeoffs for the architecture were examined including the number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply-accumulate operations. Using the MediaBench benchmark suite, we tested our methodology and architecture to accelerate software. Our combined VLIW processor with hardware functions was compared to that of software executing on a RISC processor, specifically the soft core embedded NIOS II processor. For software kernels converted into hardware functions, we show a hardware performance multiplier of up to 230 times that of software with an average 63 times faster. For the entire application in which only a portion of the software is converted to hardware, the performance improvement is as much as 30X times faster than the nonaccelerated application, with a 12X improvement on average.

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

“…We added the Sobel (sob) and Laplace (lap) edge detection algorithms to the benchmark suite. Using the SuperCISC compilation flow [9], computational kernels were extracted for these applications and converted into SDFGs, which we used as our benchmark circuits. These SDFGs were then mapped to the fabric model using the IP program, constraint program, and greedy heuristic as described in Section 4.…”

“…loops) that require large portions of the application runtime, called kernels, while assigning the control-intensive portion of the code to a core processor. These kernels are converted into entirely combinational hardware functions generated automatically from the C using a design automation flow [9]. Using hardware predication, a Control Data Flow Graph (CDFG) can be converted into a Super Data Flow Graph (SDFG) [9].…”

“…These kernels are converted into entirely combinational hardware functions generated automatically from the C using a design automation flow [9]. Using hardware predication, a Control Data Flow Graph (CDFG) can be converted into a Super Data Flow Graph (SDFG) [9]. SDFG based hardware functions operate asynchronously from the processor core.…”

Greedy Algorithms for Mapping onto a Coarse-grained Reconfigurable Fabric

“…Our group has developed the SuperCISC reconfigurable hardwa r e fa br ic t o h a ve l owenergy consumption properties compared to existing reconfigurable devices such as FPGAs Jones et al, 2008;Mehta et al, , 2007Mehta et al, , 2008. To execute an application on the SuperCISC fabric, the software kernels are converted into entirely combinational hardware functions represented by DFGs, generated automatically from C using a design automation flow (Jones et al, 2005Hoare et al, 2006;. Stripe-based hardware fabrics are designed to easily map DFGs from the application into the device.…”

Design space exploration for low-power reconfigurable fabrics

“…The SuperCISC processor was developed with a 4-way very long instruction word (VLIW) core with a shared register file [8]. The idea is to accelerate the high incidence code segments (e.g.…”