2022
DOI: 10.1016/j.nima.2022.166548
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Rate-capability of the VMM3a front-end in the RD51 Scalable Readout System

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Cited by 10 publications
(21 citation statements)
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“…For the amplitude, a clock-less 10-bit current-mode domino ADC is used [3]. For the time, a 12-bit reference clock counter is used for the rough time stamping (typical values of the adjustable clock period [4] are 22.5 ns or 25 ns). It is combined with a Time-to-Amplitude Converter (TAC) for fine time stamping, which starts once the peak is found and stops at the falling edge of the next clock cycle [3].…”
Section: Integration Of the Vmm3a Into The Srsmentioning
confidence: 99%
See 3 more Smart Citations
“…For the amplitude, a clock-less 10-bit current-mode domino ADC is used [3]. For the time, a 12-bit reference clock counter is used for the rough time stamping (typical values of the adjustable clock period [4] are 22.5 ns or 25 ns). It is combined with a Time-to-Amplitude Converter (TAC) for fine time stamping, which starts once the peak is found and stops at the falling edge of the next clock cycle [3].…”
Section: Integration Of the Vmm3a Into The Srsmentioning
confidence: 99%
“…In case a channel contains a hit 3 , a token is sent and the data flag is detected. Afterwards, the data transmission is started with maximally 180 MHz dual edge transmission [4]. The hit is written into a buffer on the Spartan-6, where two empty bits are added to the hit for the 8b/10b encoding.…”
Section: Integration Of the Vmm3a Into The Srsmentioning
confidence: 99%
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“…This small prototype is read out with two RD51 VMM3a hybrids each in x and y directions 1b. Two VMM3a ASICs [22,23] with 64 channels per chip are mounted on a RD51 VMM3a hybrid [24,25], resulting in 128 channels per hybrid. The Scalable Readout System (SRS) [26] serves as readout system to acquire the data from the RD51 [27] VMM3a hybrids.…”
Section: The Nmx Detector Prototypementioning
confidence: 99%