RDE-based transistor-level gate simulation for statistical static timing analysis

Lecture Notes in Computer Science

et al. 2013

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Abstract. Accurate timing analysis of digital integrated circuits is becoming harder to achieve with current and future CMOS technologies. The shrinking feature sizes lead to increasingly important local process variations (PV), making existing methods like corner-based static timing analysis (STA) yield overly pessimistic results. In this paper we propose a general purpose statistical circuit simulator for accurate timing analysis. A statistical simplified transistor model (SSTM) is used as the simulator's building block, allowing accurate simulation of sequential circuits while fast statistical analysis is achieved by solving a system of random differential equations (RDE), thus avoiding time-consuming Monte Carlo simulations. The conducted experiments show the accurate calculation of crossing time statistical moments for several sequential cells using 45 nm CMOS technology.

Section: Introductionmentioning

confidence: 93%

Direct Statistical Simulation of Timing Properties in Sequential Circuits

Rodríguez

Lecture Notes in Computer Science

et al. 2013

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“…3) Direct calculation based on Markovian process assumption. After calculating the nominal voltage and voltage sensitivities with respect to process variations, the delay distribution is calculated by assuming that the voltage at every time point is a Markovian stochastic process due to the numerical integration method [13], [30], [31]. In order to calculate the distribution of a crossing time, the joint probability of voltage at different time steps is calculated by using the bivariate normal distribution formula, which is erroneous when the Gaussian distribution assumption for voltages is inaccurate.…”

Section: Statistical Delay Calculationmentioning

confidence: 99%

“…Extending our previous work published in [30]- [32], this paper adds a more general statistical delay calculation method. Similarly, the linearity limitation encountered in [30]- [32] is overcome by using a PWL-RDE based method.…”

Section: Introductionmentioning

confidence: 99%

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Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver

Rodríguez

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

et al. 2014

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Abstract-To improve the accuracy of static timing analysis, the traditional nonlinear delay models are increasingly replaced by more physical gate models, such as current source models and transistor-level gate models. However, the extension of these accurate gate models for statistical timing analysis is still challenging. In this paper, we propose a novel statistical timing analysis method based on transistor-level gate models.

“…As we are moving towards nanometer technology, variations in process, voltage, and temperature are increasing, causing significant uncertainty in the delay estimation [1] and greatly impacting the yield [2]. As a consequence, various statistical static timing analysis (SSTA) algorithms [3][4][5] have been proposed to compute the statistical variations of timing performance due to the underlying process parameters.…”

Section: Introductionmentioning

confidence: 99%

Accuracy consideration of a non-Gaussian interconnect delay model for submicron CMOS statistical static timing analysis

The 4th IEEE International NanoElectronics Conference

Berkelaar

et al. 2011

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In submicron CMOS technology, due to the nonlinearity of the mapping from variation sources to the gate/wire delay, the distribution of the delay is no longer Gaussian. As the widening of process variability calls for accurate non-Gaussian timing models, their deployment requires well-controlled characterization techniques to cope with the complexity and scalability. In this paper, we present a corresponding analysis for the underlying interconnect timing model characterization infrastructure of statistical timing analysis. As the experimental results indicate, the non-Gaussian quadratic interconnect timing model is accurate within 1% error of the corresponding Monte Carlo simulation.