Re-Examination of Vth Window and Reliability in HfO2 FeFET Based on the Direct Extraction of Spontaneous Polarization and Trap Charge during Memory Operation

Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model

“…Please note that our pulse measurement setup allows about 100ns with 10ns resolution, avoiding deformation of the pulse waveform in our measurement range. For the erase characteristics with high voltage and long width, the V th becomes small which can be partly due to the hole trapping near the interface between Si and the IL [17,25]. Whereas the program characteristics does not show such behavior because the electron trapping occurs near the border trap between the IL and the HZO layer which compensates and stabilizes the spontaneous polarization charge in our measurement range [16,17].…”

“…the FE model, the NLS model [10][11][12][13][14] and the charge-trap model in gate oxide [15][16][17]. This paper is an extended version of the previous conference proceedings [18] by adding detail descriptions of the technical contents, physical analysis, and electrical characterization.…”

Memory Window in Ferroelectric Field-Effect Transistors: Analytical Approach

“…which indicates that E IL t IL = -σ 0 t IL /ε IL ε 0 , (12), and ( 14) are still valid. In other words, the following discussion is also applicable for MFIS-and MFMIS-FeFETs with additional charges at the ferroelectric/interlayer interface.…”

“…S. L. Miller and P. J. McWhorter [8] have summarized a set of the governing equations of FeFETs, but the behavior of MW has not been sufficiently discussed. Most research works discussing about MW so far have been studied through self-consistent simulations solving a set of governing equations [10][11][12][13]; however, such a numerical approach provides limited information since the role of each material parameter as well as the underlying physical mechanism is difficult to interpret accurately. One approximate expression MW = 2EctFE(1−EcεFEε0/ηPs) (P s : spontaneous polarization; η: squareness of hysteresis loop; t FE : ferroelectric thickness; ε 0 : vacuum permittivity) has been proposed by Lue et al [14], but this expression only holds at large P s otherwise the expression will be unrealistically negative.…”

“…It should be noted that the suitable P r may be deviated from (10) if the endurance and retention issues in practical devices have to be considered. Too large P r may result in a poor endurance property as it induces enormous interface charges which degrades FET interface [10,12,20,21]. In this case, smaller P r with some MW penalty can be preferable to mitigate the endurance degradation.…”