Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications

Elangovan, M.; Sharma, Kulbhushan; Sachdeva, Ashish; Gupta, Lipika

doi:10.1007/s00034-023-02529-6

Cited by 9 publications

(2 citation statements)

References 39 publications

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“…The proposed 8 T SRAM cell design has been compared to other SRAM designs that have been published in the literature. For this comparative analysis, the following SRAM designs have been selected: C6T [37], bitline powered 8 T (BLP8T) [38], Mani's 10 T [39], and low power 8 T (LP8T) [40]. These SRAM designs have been chosen for comparison because they have been recently published, based on 32-nm CNTFET technology, employ 8-10 transistors, and have read and write assist techniques.…”

Section: Discussion Of Simulation Resultsmentioning

confidence: 99%

“…Nevertheless, the suggested cell purports to better improve RSNM by employing multi-threshold CNTFETs instead of an isolated read path, which necessitates additional transistors, control signals, or even bitlines and broadens the existing leakage current path. To minimize the leakage current as much as possible, the proposed cell incorporates a high-V th M5 transistor between the power-V DD rail and the source terminals of the pull-up network of the CCI [38][39][40].…”

Section: T Sram Suggested Designmentioning

confidence: 99%

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Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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Recently, carbon nanotube field-effect transistors (CNTFETs) have garnered significant attention from VLSI engineers due to their exceptional electrical properties. This paper proposes a novel high-speed, low-power eight-transistor (8 T) static random-access memory (SRAM) cell based on 32-nm CNTFET technology. The SRAM cell was simulated using the HSPICE tool with a VDD of 0.9 V. The high-speed and low-power characteristics of the SRAM design are attributed to the high subthreshold slope and high carrier mobility of metal-oxide-semiconductor field-effect transistor (MOSFET)-like CNTFETs utilized in the simulations. The implementation of dual threshold transistors, coupled with a transmission gate for bitline access, contributes to the enhanced performance. Key performance metrics such as noise margins, power consumption, delay, and SRAM electrical quality metric (SEQM) of the proposed SRAM have been evaluated and compared with existing CNTFET-based SRAM designs. The proposed cell demonstrates reductions of 73.73%, 43.18%, and 58.70% in read power, write power, and hold power, respectively, compared to the lowest respective power values of other examined SRAM designs. The proposed SRAM ranks second, third, and second in write static noise margin (WSNM), hold static noise margin (HSNM), and read static noise margin (RSNM), respectively, among other designs. Additionally, the proposed SRAM exhibits the least sensitivity to parametric variations compared to other designs. The SEQM, which provides a comprehensive assessment of access times, noise margins, and power usage for the SRAM cell, has been calculated. The SEQM of the proposed SRAM is 10.6, 1.89, 13.15, and 1.82 times higher than that of C6T, BLP8T, Mani’s 10 T, and LP8T, respectively.

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Section: Discussion Of Simulation Resultsmentioning

confidence: 99%

Section: T Sram Suggested Designmentioning

confidence: 99%

Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

View full text Add to dashboard Cite

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Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology

Juneja,

Elangovan,

Sharma

2024

Int J Numerical Modelling

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The error tolerance nature of the digital multimedia applications enables the implementation of approximate digital circuits to achieve the benefits of high speed of operation and low power consumption. This paper proposes a static approximate modified mirror full adder (SAMM‐FA) circuit designed using logic level approximation to reduce the number of transistors in the circuit. Owing to the balanced electrical characteristics, better stability and higher on‐current to off‐current ratio (Ion/Ioff), 32 nm carbon nanotube field effect transistor (CNTFET) technology has been used for implementing the proposed circuit in the Cadence Virtuoso tool. Featuring only 10 transistors and operating at a supply voltage of 0.5 V, the proposed SAMM‐FA has a low power dissipation of just 4.14 nW, and propagation delay of just 3.82 ps. The power delay product and energy delay product figure of merits of the proposed circuit are found to be excellent when compared with the contemporary designs.

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One-Sided Schmitt-Trigger-Based Low Power Read Decoupled 11T CNTFET SRAM with Improved Stability

Elangovan,

Sharma,

Sachdeva

et al. 2024

Circuits Syst Signal Process

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Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications

Cited by 9 publications

References 39 publications

Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology

One-Sided Schmitt-Trigger-Based Low Power Read Decoupled 11T CNTFET SRAM with Improved Stability

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