Read SNM free SRAM cell design in deep submicron technology

Study of SRAM Standby Leakage Reduction Techniques for Deep-submicron CMOS Technology

“…Read SNM and hold SNM of SRAM bitcell are the measures of its stability in respective read and standby modes of the cell [12]. To optimize the yield of memory chip, the impact of process variation on the design metrics should be taken up front during the design phase [17].…”

“…(1) VDD lowering (VDDL) (2) VSS rising (VSSR) (3) Bitline floating (BLF) (4) Reversing body bias (RBB) [10,14]. In this paper, firstly we have designed a 6T SRAM bitcell in 45 nm CMOS technology node, characterized by parameters like read SNM (static noise margin), hold SNM, WM (write margin) and read current [12]. Then, we have analyzed the standby leakage composition of this cell with temperature.…”

A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques

“…The reduction in V MIN of the SRAM cell for scaled devices is limited because of the local threshold voltage variations resulting from random dopant fluctuations and lithographic-dependent patterns have been increasing [1]. Also, with the increased threshold voltage variations in scaled transistors the access-disturbance margin (ADM) [2] and write margin (WM) [3] of the SRAM bitcell have been degrading. Process variations make SRAM design less predictable and controllable, moreover the SRAM design space in terms of prediction and control degrades further as supply voltage (V DD ) scales down [5].…”