Read Static Noise Margin Decrease of 65-nm 6-T SRAM Cell Induced by Total Ionizing Dose

Zheng, Qiwen; Cui, Jiangwei; Yu, Xuefeng; Lü, Wei; He, Chengfa; Ma, Teng; Zhao, Jinghao; Ren, Dazhong; Guo, Qi

doi:10.1109/tns.2017.2786227

Cited by 12 publications

(2 citation statements)

References 23 publications

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“…The pre-charge circuit gives high voltage to both the BL = '1' and BLB = '1' during the read operation. There is no BL voltage discharge if the proposed cell has a high value [19][20].…”

Section: T Rhbd Sram Cellmentioning

confidence: 99%

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Gavaskar¹,

Sivaranjani²,

Elango³

et al. 2022

Wireless Pers Commun

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One of the most critical functions of a computer is memory, as it would be impossible for it to function e ciently without it. The main memory of a computer is known as Random Access Memory (RAM). It stores operating system software, applications, and other data for the central processor unit (CPU) to perform operations swiftly and e ciently. Unfortunately, traditional static RAM (SRAMs) in aerospace applications suffers from high soft error issues such as Single Event Upset (SEU). To overcome the soft error problems, many Radiation-Hardened-Based Designs (RHBD) and Radiation-Hardened-Polar Designs (RHPD) have been developed, such as 12T We-Quatro, twelve-transistor (12T) Dice SRAM cells, and so on. However, they consume more total and static power, as well as have more delay and area. In this article, an RHPD and RHBD 12T SRAM cell is proposed to reduce power dissipation and area overhead. Compared to RHPD, the RHBD 12T SRAM cell devours less total and static power, and RHPD cells have less delay. The proposed SRAM cell is implemented in the 32 x 32 array architecture. The power consumption of a 32 x 32 SRAM array with a 12T RHBD SRAM cell is 1.33mW, which is 10.1% less than a 32 x 32 SRAM array with a 12T RHPD SRAM array is 4.23mW. Cadence virtuoso 6.1.5 at 45 nm Generic Process Design Kit (GPDK) technology le is used to simulate the comparative analysis for the SRAM cell.

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“…The pre-charge circuit gives high voltage to both the BL = '1' and BLB = '1' during the read operation. There is no BL voltage discharge if the proposed cell has a high value [19][20].…”

Section: T Rhbd Sram Cellmentioning

confidence: 99%

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Gavaskar¹,

Sivaranjani²,

Elango³

et al. 2022

Wireless Pers Commun

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show abstract

“…To riddle out this challenge, multiple structures have been proposed in the past. Read static noise margin (RSNM) can be enhanced by decoupling of read and write ports as in 6 T (Seevinck et al , 1987; Takashima et al , 2018; Zheng et al , 2017) and 7 transistors (7 T) (Aly and Bayoumi, 2007) SRAM cells. This has been a feasible way to enhance noise margin, but the consequence turns out to be an increment in the area and dissolute read performance due to single-ended sensing.…”

Section: Introductionmentioning

confidence: 99%

Design and mathematical analysis of a 7T SRAM cell with enhanced read SNM using PMOS as an access transistor

Mishra

Vaithiyanathan

Pal

et al. 2021

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Purpose This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell. Design/methodology/approach The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate. Findings Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively. Originality/value The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

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Analysis of Clock Tree Buffer Degradation Caused by Radiation

Watanabe

2024

Lecture Notes in Computer Science

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Read Static Noise Margin Decrease of 65-nm 6-T SRAM Cell Induced by Total Ionizing Dose

Cited by 12 publications

References 23 publications

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Design and mathematical analysis of a 7T SRAM cell with enhanced read SNM using PMOS as an access transistor

Analysis of Clock Tree Buffer Degradation Caused by Radiation

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